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The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.

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Remove the offending logic and update the test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127843 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-03-18 00:38:03 +00:00
parent f3e6774880
commit 5e5a40867a
2 changed files with 5 additions and 13 deletions
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12
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
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@ -962,11 +962,7 @@ static bool DisassembleThumb1Br(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned Imm11 = getT1Imm11(insn); unsigned Imm11 = getT1Imm11(insn);
// When executing a Thumb instruction, PC reads as the address of the current MI.addOperand(MCOperand::CreateImm(SignExtend32<12>(Imm11 << 1)));
// instruction plus 4. The assembler subtracts 4 from the difference between
// the branch instruction and the target address, disassembler has to add 4 to
// to compensate.
MI.addOperand(MCOperand::CreateImm(SignExtend32<12>(Imm11 << 1) + 4));
NumOpsAdded = 1; NumOpsAdded = 1;
@ -1747,11 +1743,7 @@ static bool DisassembleThumb2BrMiscCtrl(MCInst &MI, unsigned Opcode,
Offset = decodeImm32_BLX(insn); Offset = decodeImm32_BLX(insn);
break; break;
} }
// When executing a Thumb instruction, PC reads as the address of the current MI.addOperand(MCOperand::CreateImm(Offset));
// instruction plus 4. The assembler subtracts 4 from the difference between
// the branch instruction and the target address, disassembler has to add 4 to
// to compensate.
MI.addOperand(MCOperand::CreateImm(Offset + 4));
// This is an increment as some predicate operands may have been added first. // This is an increment as some predicate operands may have been added first.
NumOpsAdded += 1; NumOpsAdded += 1;

6
test/MC/Disassembler/ARM/thumb-tests.txt
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@ -6,10 +6,10 @@
# CHECK: adcs r0, r0, #1 # CHECK: adcs r0, r0, #1
0x50 0xf1 0x01 0x00 0x50 0xf1 0x01 0x00
# CHECK: b #34 # CHECK: b #30
0x0f 0xe0 0x0f 0xe0
# CHECK: b.w #-12 # CHECK: b.w #-16
0xff 0xf7 0xf8 0xaf 0xff 0xf7 0xf8 0xaf
# CHECK: bfi r2, r10, #0, #1 # CHECK: bfi r2, r10, #0, #1
@ -128,5 +128,5 @@
# CHECK: msr cpsr_fc, r0 # CHECK: msr cpsr_fc, r0
0x80 0xf3 0x00 0x89 0x80 0xf3 0x00 0x89
# CHECK: blx #0 # CHECK: blx #-4
0xff 0xf7 0xfe 0xef 0xff 0xf7 0xfe 0xef