From 5e95e642e9d072beddb6c75724b7064ba4d45f85 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Thu, 23 Jan 2014 10:31:31 +0000 Subject: [PATCH] [mips][sched] Split IIStore into II_S[BHWD], II_S[WD][LR], and II_SAVE No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199876 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips16InstrInfo.td | 12 ++++++------ lib/Target/Mips/Mips64InstrInfo.td | 16 ++++++++-------- lib/Target/Mips/MipsInstrInfo.td | 10 +++++----- lib/Target/Mips/MipsSchedule.td | 24 ++++++++++++++++++++---- 4 files changed, 39 insertions(+), 23 deletions(-) diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index b604b69bd42..11166c45a88 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -985,7 +985,7 @@ def RestoreX16: // def Save16: FI8_SVRS16<0b1, (outs), (ins variable_ops), - "", [], IIStore >, MayStore { + "", [], II_SAVE >, MayStore { let isCodeGenOnly = 1; let Uses = [SP]; let Defs = [SP]; @@ -993,7 +993,7 @@ def Save16: def SaveX16: FI8_SVRS16<0b1, (outs), (ins variable_ops), - "", [], IIStore >, MayStore { + "", [], II_SAVE >, MayStore { let isCodeGenOnly = 1; let Uses = [SP]; let Defs = [SP]; @@ -1004,7 +1004,7 @@ def SaveX16: // To store a byte to memory. // def SbRxRyOffMemX16: - FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore; + FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, II_SB>, MayStore; // // Format: SEB rx MIPS16e @@ -1142,7 +1142,7 @@ def SelTBtneZSltiu: SeliT<"btnez", "sltiu">; // To store a halfword to memory. // def ShRxRyOffMemX16: - FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore; + FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, II_SH>, MayStore; // // Format: SLL rx, ry, sa MIPS16e @@ -1278,7 +1278,7 @@ def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>; // To store a word to memory. // def SwRxRyOffMemX16: - FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore; + FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, II_SW>, MayStore; // // Format: SW rx, offset(sp) MIPS16e @@ -1286,7 +1286,7 @@ def SwRxRyOffMemX16: // To store an SP-relative word to memory. // def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins - <0b11010, "sw", IIStore>, MayStore; + <0b11010, "sw", II_SW>, MayStore; // // diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 77973560a9b..54d8e35b724 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -126,27 +126,27 @@ def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>; def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>; def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>; def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>; -def SB64 : Store<"sb", GPR64Opnd, truncstorei8, IIStore>, LW_FM<0x28>; -def SH64 : Store<"sh", GPR64Opnd, truncstorei16, IIStore>, LW_FM<0x29>; -def SW64 : Store<"sw", GPR64Opnd, truncstorei32, IIStore>, LW_FM<0x2b>; +def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>; +def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>; +def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>; } def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>; def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>; -def SD : Store<"sd", GPR64Opnd, store, IIStore>, LW_FM<0x3f>; +def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>; /// load/store left/right let isCodeGenOnly = 1 in { def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>; def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>; -def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, IIStore>, LW_FM<0x2a>; -def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, IIStore>, LW_FM<0x2e>; +def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>; +def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>; } def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>; def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>; -def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, IIStore>, LW_FM<0x2c>; -def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, IIStore>, LW_FM<0x2d>; +def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>; +def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>; /// Load-linked, Store-conditional def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 60e26683ace..19cb105d283 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -976,16 +976,16 @@ def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel, def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>; def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, LW_FM<0x23>; -def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>; -def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>; -def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>; +def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>; +def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>; +def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>; /// load/store left/right let Predicates = [NotInMicroMips] in { def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>; def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>; -def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>; -def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>; +def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>; +def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>; } def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM; diff --git a/lib/Target/Mips/MipsSchedule.td b/lib/Target/Mips/MipsSchedule.td index 34f7d7f677e..b6a9652c045 100644 --- a/lib/Target/Mips/MipsSchedule.td +++ b/lib/Target/Mips/MipsSchedule.td @@ -17,7 +17,6 @@ def IMULDIV : FuncUnit; // Instruction Itinerary classes used for Mips //===----------------------------------------------------------------------===// def IIAlu : InstrItinClass; -def IIStore : InstrItinClass; def IIBranch : InstrItinClass; def IIPseudo : InstrItinClass; @@ -75,10 +74,10 @@ def II_LHU : InstrItinClass; def II_LUI : InstrItinClass; def II_LUXC1 : InstrItinClass; def II_LW : InstrItinClass; -def II_LWU : InstrItinClass; def II_LWC1 : InstrItinClass; def II_LWL : InstrItinClass; def II_LWR : InstrItinClass; +def II_LWU : InstrItinClass; def II_LWXC1 : InstrItinClass; def II_MADD : InstrItinClass; def II_MADDU : InstrItinClass; @@ -121,15 +120,21 @@ def II_NMSUB_S : InstrItinClass; def II_NOR : InstrItinClass; def II_OR : InstrItinClass; def II_ORI : InstrItinClass; -def II_RESTORE : InstrItinClass; def II_RDHWR : InstrItinClass; +def II_RESTORE : InstrItinClass; def II_ROTR : InstrItinClass; def II_ROTRV : InstrItinClass; def II_ROUND : InstrItinClass; +def II_SAVE : InstrItinClass; +def II_SB : InstrItinClass; +def II_SD : InstrItinClass; def II_SDC1 : InstrItinClass; +def II_SDL : InstrItinClass; +def II_SDR : InstrItinClass; def II_SDXC1 : InstrItinClass; def II_SEB : InstrItinClass; def II_SEH : InstrItinClass; +def II_SH : InstrItinClass; def II_SLL : InstrItinClass; def II_SLLV : InstrItinClass; def II_SLTI_SLTIU : InstrItinClass; // slti and sltiu @@ -144,7 +149,10 @@ def II_SUBU : InstrItinClass; def II_SUB_D : InstrItinClass; def II_SUB_S : InstrItinClass; def II_SUXC1 : InstrItinClass; +def II_SW : InstrItinClass; def II_SWC1 : InstrItinClass; +def II_SWL : InstrItinClass; +def II_SWR : InstrItinClass; def II_SWXC1 : InstrItinClass; def II_TRUNC : InstrItinClass; def II_XOR : InstrItinClass; @@ -206,7 +214,15 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData]>, InstrItinData]>, InstrItinData]>, - InstrItinData]>, + InstrItinData]>, + InstrItinData]>, + InstrItinData]>, + InstrItinData]>, + InstrItinData]>, + InstrItinData]>, + InstrItinData]>, + InstrItinData]>, + InstrItinData]>, InstrItinData]>, InstrItinData]>, InstrItinData]>,