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R600/SI: Fix losing chain when fixing reg class of loads.

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The lost chain resulting in earlier side effecting nodes
being deleted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217561 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
2014-09-10 23:26:19 +00:00
parent c8256c4dcb
commit 5ee5d45e7e
2 changed files with 40 additions and 6 deletions
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20
lib/Target/R600/SIISelLowering.cpp
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@@ -2004,12 +2004,20 @@ MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
return N;
}
ConstantSDNode *Offset = cast<ConstantSDNode>(N->getOperand(1));
SDValue Ops[] = {
SDValue(DAG.getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::i128,
DAG.getConstant(0, MVT::i64)), 0),
N->getOperand(0),
DAG.getConstant(Offset->getSExtValue() << 2, MVT::i32)
};
MachineSDNode *RSrc = DAG.getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL,
MVT::i128,
DAG.getConstant(0, MVT::i64));
SmallVector<SDValue, 8> Ops;
Ops.push_back(SDValue(RSrc, 0));
Ops.push_back(N->getOperand(0));
Ops.push_back(DAG.getConstant(Offset->getSExtValue() << 2, MVT::i32));
// Copy remaining operands so we keep any chain and glue nodes that follow
// the normal operands.
for (unsigned I = 2, E = N->getNumOperands(); I != E; ++I)
Ops.push_back(N->getOperand(I));
return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
}
}