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[Hexagon] Adding a number of additional multiply forms with tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224282 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
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bc541ae238
commit
5f702749c1
@ -2034,6 +2034,10 @@ class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC,
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let Inst{4-0} = dst;
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}
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class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp,
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bit isSat = 0, bit isRnd = 0 >
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: T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>;
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class T_MType_rr1 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
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bit isSat = 0, bit isRnd = 0 >
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: T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>;
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@ -2045,8 +2049,10 @@ class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
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let CextOpcode = "mpyi", InputType = "reg", isCodeGenOnly = 0 in
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def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel;
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let isCodeGenOnly = 0 in
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let isCodeGenOnly = 0 in {
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def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>;
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def M2_mpyu_up : T_MType_rr1 <"mpyu", 0b010, 0b001>;
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}
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let isCodeGenOnly = 0 in
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def M2_dpmpyss_rnd_s0 : T_MType_rr1 <"mpy", 0b001, 0b001, 0, 1>;
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@ -2056,6 +2062,125 @@ def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">;
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def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">;
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}
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// V4 Instructions
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let isCodeGenOnly = 0 in {
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def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>;
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def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>;
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def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">;
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def M2_hmmpyl_s1 : T_MType_rr2 <"mpy", 0b101, 0b001, 1, 0, ".l">;
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}
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def: Pat<(i32 (mul I32:$src1, I32:$src2)), (M2_mpyi I32:$src1, I32:$src2)>;
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def: Pat<(i32 (mulhs I32:$src1, I32:$src2)), (M2_mpy_up I32:$src1, I32:$src2)>;
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def: Pat<(i32 (mulhu I32:$src1, I32:$src2)), (M2_mpyu_up I32:$src1, I32:$src2)>;
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let hasNewValue = 1, opNewValue = 0 in
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class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern>
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: MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
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"$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" ,
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pattern, "", M_tc_3x_SLOT23> {
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bits<5> Rd;
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bits<5> Rs;
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bits<8> u8;
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let IClass = 0b1110;
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let Inst{27-24} = 0b0000;
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let Inst{23} = isNeg;
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let Inst{13} = 0b0;
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let Inst{4-0} = Rd;
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let Inst{20-16} = Rs;
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let Inst{12-5} = u8;
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}
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let isExtendable = 1, opExtentBits = 8, opExtendable = 2, isCodeGenOnly = 0 in
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def M2_mpysip : T_MType_mpy_ri <0, u8Ext,
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[(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u8ExtPred:$u8))]>;
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let isCodeGenOnly = 0 in
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def M2_mpysin : T_MType_mpy_ri <1, u8Imm,
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[(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
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u8ImmPred:$u8)))]>;
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// Assember mapped to M2_mpyi
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let isAsmParserOnly = 1 in
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def M2_mpyui : MInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst = mpyui($src1, $src2)">;
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// Rd=mpyi(Rs,#m9)
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// s9 is NOT the same as m9 - but it works.. so far.
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// Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8)
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// depending on the value of m9. See Arch Spec.
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
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CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1 in
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def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
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"$dst = mpyi($src1, #$src2)",
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[(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
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s9ExtPred:$src2))]>, ImmRegRel;
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let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3,
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InputType = "imm" in
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class T_MType_acc_ri <string mnemonic, bits<3> MajOp, Operand ImmOp,
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list<dag> pattern = []>
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: MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3),
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"$dst "#mnemonic#"($src2, #$src3)",
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pattern, "$src1 = $dst", M_tc_2_SLOT23> {
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bits<5> dst;
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bits<5> src2;
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bits<8> src3;
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let IClass = 0b1110;
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let Inst{27-26} = 0b00;
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let Inst{25-23} = MajOp;
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let Inst{20-16} = src2;
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let Inst{13} = 0b0;
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let Inst{12-5} = src3;
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let Inst{4-0} = dst;
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}
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let InputType = "reg", hasNewValue = 1 in
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class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp,
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bit isSwap = 0, list<dag> pattern = [], bit hasNot = 0,
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bit isSat = 0, bit isShift = 0>
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: MInst < (outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"$dst "#mnemonic#"($src2, "#!if(hasNot, "~$src3)","$src3)")
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#!if(isShift, ":<<1", "")
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#!if(isSat, ":sat", ""),
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pattern, "$src1 = $dst", M_tc_2_SLOT23 > {
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bits<5> dst;
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bits<5> src2;
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bits<5> src3;
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let IClass = 0b1110;
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let Inst{27-24} = 0b1111;
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let Inst{23-21} = MajOp;
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let Inst{20-16} = !if(isSwap, src3, src2);
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let Inst{13} = 0b0;
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let Inst{12-8} = !if(isSwap, src2, src3);
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let Inst{7-5} = MinOp;
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let Inst{4-0} = dst;
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}
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let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
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def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8Ext,
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[(set (i32 IntRegs:$dst),
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(add (mul IntRegs:$src2, u8ExtPred:$src3),
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IntRegs:$src1))]>, ImmRegRel;
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def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0,
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[(set (i32 IntRegs:$dst),
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(add (mul IntRegs:$src2, IntRegs:$src3),
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IntRegs:$src1))]>, ImmRegRel;
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}
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let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in
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def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>;
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// Multiply and use lower result.
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// Rd=+mpyi(Rs,#u8)
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
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@ -2099,16 +2224,6 @@ def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
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(i32 IntRegs:$src1)))],
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"$src1 = $dst">, ImmRegRel;
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// Rx+=mpyi(Rs,Rt)
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let CextOpcode = "MPYI_acc", InputType = "reg" in
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def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"$dst += mpyi($src2, $src3)",
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[(set (i32 IntRegs:$dst),
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(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
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(i32 IntRegs:$src1)))],
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"$src1 = $dst">, ImmRegRel;
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// Rx-=mpyi(Rs,#u8)
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let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8 in
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def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
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@ -1,7 +1,17 @@
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# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
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0xf1 0xc3 0x15 0xe0
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# CHECK: r17 =+ mpyi(r21, #31)
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0xf1 0xc3 0x95 0xe0
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# CHECK: r17 =- mpyi(r21, #31)
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0xf1 0xc3 0x15 0xe1
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# CHECK: r17 += mpyi(r21, #31)
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0xf1 0xc3 0x95 0xe1
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# CHECK: r17 -= mpyi(r21, #31)
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0x11 0xdf 0x15 0xed
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# CHECK: r17 = mpyi(r21, r31)
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0x11 0xdf 0x15 0xef
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# CHECK: r17 += mpyi(r21, r31)
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0x10 0xdf 0x95 0xe6
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# CHECK: r17:16 += mpy(r21.l, r31.l):<<1
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0x30 0xdf 0x95 0xe6
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@ -122,10 +132,20 @@
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# CHECK: r17 -= mpyu(r21.h, r31.l):<<1
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0x71 0xdf 0xf5 0xee
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# CHECK: r17 -= mpyu(r21.h, r31.h):<<1
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0x31 0xdf 0x15 0xed
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# CHECK: r17 = mpy(r21, r31)
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0x31 0xdf 0x35 0xed
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# CHECK: r17 = mpy(r21, r31):rnd
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0x31 0xdf 0x55 0xed
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# CHECK: r17 = mpyu(r21, r31)
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0x31 0xdf 0x75 0xed
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# CHECK: r17 = mpysu(r21, r31)
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0x11 0xdf 0xb5 0xed
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# CHECK: r17 = mpy(r21, r31.h):<<1:sat
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0x31 0xdf 0xb5 0xed
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# CHECK: r17 = mpy(r21, r31.l):<<1:sat
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0x11 0xdf 0xf5 0xed
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# CHECK: r17 = mpy(r21, r31):<<1:sat
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0x91 0xdf 0xb5 0xed
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# CHECK: r17 = mpy(r21, r31.h):<<1:rnd:sat
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0x91 0xdf 0xf5 0xed
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