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s/std::vector/SmallVector/

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118648 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-11-09 23:28:44 +00:00
parent 037b5be15a
commit 5fa22a1975
1 changed files with 11 additions and 12 deletions
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23
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -128,7 +128,7 @@ class ARMOperand : public MCParsedAsmOperand {
} Reg; } Reg;
struct { struct {
std::vector<unsigned> *Registers; SmallVector<unsigned, 32> *Registers;
} RegList; } RegList;
struct { struct {
@ -203,7 +203,7 @@ public:
return Reg.RegNum; return Reg.RegNum;
} }
const std::vector<unsigned> &getRegList() const { const SmallVectorImpl<unsigned> &getRegList() const {
assert(Kind == RegisterList && "Invalid access!"); assert(Kind == RegisterList && "Invalid access!");
return *RegList.Registers; return *RegList.Registers;
} }
@ -258,8 +258,8 @@ public:
void addRegListOperands(MCInst &Inst, unsigned N) const { void addRegListOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!"); assert(N == 1 && "Invalid number of operands!");
const std::vector<unsigned> &RegList = getRegList(); const SmallVectorImpl<unsigned> &RegList = getRegList();
for (std::vector<unsigned>::const_iterator for (SmallVectorImpl<unsigned>::const_iterator
I = RegList.begin(), E = RegList.end(); I != E; ++I) I = RegList.begin(), E = RegList.end(); I != E; ++I)
Inst.addOperand(MCOperand::CreateReg(*I)); Inst.addOperand(MCOperand::CreateReg(*I));
} }
@ -325,11 +325,11 @@ public:
} }
static ARMOperand * static ARMOperand *
CreateRegList(std::vector<std::pair<unsigned, SMLoc> > &Regs, CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
SMLoc S, SMLoc E) { SMLoc S, SMLoc E) {
ARMOperand *Op = new ARMOperand(RegisterList); ARMOperand *Op = new ARMOperand(RegisterList);
Op->RegList.Registers = new std::vector<unsigned>(); Op->RegList.Registers = new SmallVector<unsigned, 32>();
for (std::vector<std::pair<unsigned, SMLoc> >::iterator for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
I = Regs.begin(), E = Regs.end(); I != E; ++I) I = Regs.begin(), E = Regs.end(); I != E; ++I)
Op->RegList.Registers->push_back(I->first); Op->RegList.Registers->push_back(I->first);
std::sort(Op->RegList.Registers->begin(), Op->RegList.Registers->end()); std::sort(Op->RegList.Registers->begin(), Op->RegList.Registers->end());
@ -390,8 +390,8 @@ void ARMOperand::dump(raw_ostream &OS) const {
case RegisterList: { case RegisterList: {
OS << "<register_list "; OS << "<register_list ";
const std::vector<unsigned> &RegList = getRegList(); const SmallVectorImpl<unsigned> &RegList = getRegList();
for (std::vector<unsigned>::const_iterator for (SmallVectorImpl<unsigned>::const_iterator
I = RegList.begin(), E = RegList.end(); I != E; ) { I = RegList.begin(), E = RegList.end(); I != E; ) {
OS << *I; OS << *I;
if (++I < E) OS << ", "; if (++I < E) OS << ", ";
@ -465,8 +465,7 @@ ARMOperand *ARMAsmParser::ParseRegisterList() {
// Read the rest of the registers in the list. // Read the rest of the registers in the list.
unsigned PrevRegNum = 0; unsigned PrevRegNum = 0;
std::vector<std::pair<unsigned, SMLoc> > Registers; SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
Registers.reserve(32);
do { do {
bool IsRange = Parser.getTok().is(AsmToken::Minus); bool IsRange = Parser.getTok().is(AsmToken::Minus);
@ -510,7 +509,7 @@ ARMOperand *ARMAsmParser::ParseRegisterList() {
Parser.Lex(); // Eat right curly brace token. Parser.Lex(); // Eat right curly brace token.
// Verify the register list. // Verify the register list.
std::vector<std::pair<unsigned, SMLoc> >::const_iterator SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
RI = Registers.begin(), RE = Registers.end(); RI = Registers.begin(), RE = Registers.end();
unsigned HighRegNum = RI->first; unsigned HighRegNum = RI->first;