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[SystemZ] Optimize 32-bit FPR<->GPR moves for z196 and above

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Floats are stored in the high 32 bits of an FPR, and the only GPR<->FPR
transfers are full-register transfers.  This patch optimizes GPR<->FPR
float transfers when the high word of a GPR is directly accessible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191764 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford 2013-10-01 14:31:11 +00:00
parent c269c4f505
commit 5fb8d3144f
1 changed files with 18 additions and 7 deletions
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25
lib/Target/SystemZ/SystemZISelLowering.cpp
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@ -1561,11 +1561,19 @@ SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
EVT InVT = In.getValueType(); EVT InVT = In.getValueType();
EVT ResVT = Op.getValueType(); EVT ResVT = Op.getValueType();
SDValue Shift32 = DAG.getConstant(32, MVT::i64);
if (InVT == MVT::i32 && ResVT == MVT::f32) { if (InVT == MVT::i32 && ResVT == MVT::f32) {
SDValue In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In); SDValue In64;
SDValue Shift = DAG.getNode(ISD::SHL, DL, MVT::i64, In64, Shift32); if (Subtarget.hasHighWord()) {
SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, Shift); SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
MVT::i64);
In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
MVT::i64, SDValue(U64, 0), In);
} else {
In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
DAG.getConstant(32, MVT::i64));
}
SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, return DAG.getTargetExtractSubreg(SystemZ::subreg_h32,
DL, MVT::f32, Out64); DL, MVT::f32, Out64);
} }
@ -1574,9 +1582,12 @@ SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL, SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
MVT::f64, SDValue(U64, 0), In); MVT::f64, SDValue(U64, 0), In);
SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64); SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64, Shift32); if (Subtarget.hasHighWord())
SDValue Out = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift); return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
return Out; MVT::i32, Out64);
SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
DAG.getConstant(32, MVT::i64));
return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
} }
llvm_unreachable("Unexpected bitcast combination"); llvm_unreachable("Unexpected bitcast combination");
} }