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TargetRegisterClass specifies the desired spill alignment. However, it cannot be honored if stack alignment is smaller.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30648 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-09-28 18:52:32 +00:00
parent ba9f0431f0
commit 5feaa9a707
1 changed files with 6 additions and 1 deletions
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7
lib/CodeGen/PrologEpilogInserter.cpp
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@ -190,7 +190,12 @@ void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
int FrameIdx;
if (FixedSlot == FixedSpillSlots+NumFixedSpillSlots) {
// Nope, just spill it anywhere convenient.
FrameIdx = FFI->CreateStackObject(RC->getSize(), RC->getAlignment());
unsigned Align = RC->getAlignment();
unsigned StackAlign = TFI->getStackAlignment();
// We may not be able to sastify the desired alignment specification of
// the TargetRegisterClass if the stack alignment is smaller. Use the min.
Align = std::min(Align, StackAlign);
FrameIdx = FFI->CreateStackObject(RC->getSize(), Align);
if ((unsigned)FrameIdx < MinCSFrameIndex) MinCSFrameIndex = FrameIdx;
if ((unsigned)FrameIdx > MaxCSFrameIndex) MaxCSFrameIndex = FrameIdx;
} else {