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[X86] Remove FeatureAES for 'corei7' CPU. 'corei7' should match 'nehalem' which doesn't have AES. Having AES and not PCLMUL makes 'corei7' halfway between Nehalem and Westmere.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233517 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2015-03-30 06:31:11 +00:00
parent c637444fed
commit 5ffc995ff3
1 changed files with 9 additions and 11 deletions
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20
lib/Target/X86/X86.td
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@ -273,17 +273,15 @@ def : SilvermontProc<"silvermont">;
def : SilvermontProc<"slm">; // Legacy alias. def : SilvermontProc<"slm">; // Legacy alias.
// "Arrandale" along with corei3 and corei5 // "Arrandale" along with corei3 and corei5
class NehalemProc<string Name, list<SubtargetFeature> AdditionalFeatures> class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
: ProcessorModel<Name, SandyBridgeModel, !listconcat([ FeatureSSE42,
FeatureSSE42, FeatureCMPXCHG16B,
FeatureCMPXCHG16B, FeatureSlowBTMem,
FeatureSlowBTMem, FeatureFastUAMem,
FeatureFastUAMem, FeaturePOPCNT
FeaturePOPCNT ]>;
], def : NehalemProc<"nehalem">;
AdditionalFeatures)>; def : NehalemProc<"corei7">;
def : NehalemProc<"nehalem", []>;
def : NehalemProc<"corei7", [FeatureAES]>;
// Westmere is a similar machine to nehalem with some additional features. // Westmere is a similar machine to nehalem with some additional features.
// Westmere is the corei3/i5/i7 path from nehalem to sandybridge // Westmere is the corei3/i5/i7 path from nehalem to sandybridge