From 5ffd24c49f6d78c166ee357424bf4e20f61af6bc Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Tue, 5 Mar 2013 23:22:30 +0000 Subject: [PATCH] [mips] Remove android calling convention. This calling convention was added just to handle functions which return vector of floats. The fix committed in r165585 solves the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176530 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips.td | 2 -- lib/Target/Mips/MipsCallingConv.td | 12 ------------ lib/Target/Mips/MipsSubtarget.cpp | 2 +- lib/Target/Mips/MipsSubtarget.h | 4 ---- test/CodeGen/Mips/return-vector-float4.ll | 12 ------------ 5 files changed, 1 insertion(+), 31 deletions(-) delete mode 100644 test/CodeGen/Mips/return-vector-float4.ll diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index 13266233dd3..eefb02a494c 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -44,8 +44,6 @@ def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64", "Enable n64 ABI">; def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", "Enable eabi ABI">; -def FeatureAndroid : SubtargetFeature<"android", "IsAndroid", "true", - "Target is android">; def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", "true", "Enable vector FPU instructions.">; def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true", diff --git a/lib/Target/Mips/MipsCallingConv.td b/lib/Target/Mips/MipsCallingConv.td index 8e9e4c726fa..462def76cc8 100644 --- a/lib/Target/Mips/MipsCallingConv.td +++ b/lib/Target/Mips/MipsCallingConv.td @@ -144,17 +144,6 @@ def RetCC_MipsEABI : CallingConv<[ CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>> ]>; -//===----------------------------------------------------------------------===// -// Mips Android Calling Convention -//===----------------------------------------------------------------------===// - -def RetCC_MipsAndroid : CallingConv<[ - // f32 are returned in registers F0, F2, F1, F3 - CCIfType<[f32], CCAssignToReg<[F0, F2, F1, F3]>>, - - CCDelegateTo -]>; - //===----------------------------------------------------------------------===// // Mips FastCC Calling Convention //===----------------------------------------------------------------------===// @@ -215,7 +204,6 @@ def RetCC_Mips : CallingConv<[ CCIfSubtarget<"isABI_EABI()", CCDelegateTo>, CCIfSubtarget<"isABI_N32()", CCDelegateTo>, CCIfSubtarget<"isABI_N64()", CCDelegateTo>, - CCIfSubtarget<"isAndroid()", CCDelegateTo>, CCDelegateTo ]>; diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index 75b4c98a9f5..e11e5d142b7 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -33,7 +33,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, IsLinux(true), HasSEInReg(false), HasCondMov(false), HasSwap(false), HasBitCount(false), HasFPIdx(false), InMips16Mode(false), InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), - IsAndroid(false), RM(_RM) + RM(_RM) { std::string CPUName = CPU; if (CPUName.empty()) diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index 32baa3d85ad..7a2e47ce5a9 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -95,9 +95,6 @@ protected: // HasDSP, HasDSPR2 -- supports DSP ASE. bool HasDSP, HasDSPR2; - // IsAndroid -- target is android - bool IsAndroid; - InstrItineraryData InstrItins; // The instance to the register info section object @@ -144,7 +141,6 @@ public: bool inMicroMipsMode() const { return InMicroMipsMode; } bool hasDSP() const { return HasDSP; } bool hasDSPR2() const { return HasDSPR2; } - bool isAndroid() const { return IsAndroid; } bool isLinux() const { return IsLinux; } bool useSmallSection() const { return UseSmallSection; } diff --git a/test/CodeGen/Mips/return-vector-float4.ll b/test/CodeGen/Mips/return-vector-float4.ll deleted file mode 100644 index ae10f123e4d..00000000000 --- a/test/CodeGen/Mips/return-vector-float4.ll +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: llc -march=mipsel -mattr=+android < %s | FileCheck %s - -define <4 x float> @retvec4() nounwind readnone { -entry: -; CHECK: lwc1 $f0 -; CHECK: lwc1 $f2 -; CHECK: lwc1 $f1 -; CHECK: lwc1 $f3 - - ret <4 x float> -} -