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[mips] Remove android calling convention.

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This calling convention was added just to handle functions which return vector
of floats. The fix committed in r165585 solves the problem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176530 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-03-05 23:22:30 +00:00
parent 1e3e869899
commit 5ffd24c49f
5 changed files with 1 additions and 31 deletions
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2
lib/Target/Mips/Mips.td
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@ -44,8 +44,6 @@ def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64",
"Enable n64 ABI">;
def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
"Enable eabi ABI">;
def FeatureAndroid : SubtargetFeature<"android", "IsAndroid", "true",
"Target is android">;
def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
"true", "Enable vector FPU instructions.">;
def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",

12
lib/Target/Mips/MipsCallingConv.td
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@ -144,17 +144,6 @@ def RetCC_MipsEABI : CallingConv<[
CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>>
]>;
//===----------------------------------------------------------------------===//
// Mips Android Calling Convention
//===----------------------------------------------------------------------===//
def RetCC_MipsAndroid : CallingConv<[
// f32 are returned in registers F0, F2, F1, F3
CCIfType<[f32], CCAssignToReg<[F0, F2, F1, F3]>>,
CCDelegateTo<RetCC_MipsO32>
]>;
//===----------------------------------------------------------------------===//
// Mips FastCC Calling Convention
//===----------------------------------------------------------------------===//
@ -215,7 +204,6 @@ def RetCC_Mips : CallingConv<[
CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
CCIfSubtarget<"isAndroid()", CCDelegateTo<RetCC_MipsAndroid>>,
CCDelegateTo<RetCC_MipsO32>
]>;

2
lib/Target/Mips/MipsSubtarget.cpp
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@ -33,7 +33,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
IsLinux(true), HasSEInReg(false), HasCondMov(false), HasSwap(false),
HasBitCount(false), HasFPIdx(false),
InMips16Mode(false), InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
IsAndroid(false), RM(_RM)
RM(_RM)
{
std::string CPUName = CPU;
if (CPUName.empty())

4
lib/Target/Mips/MipsSubtarget.h
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@ -95,9 +95,6 @@ protected:
// HasDSP, HasDSPR2 -- supports DSP ASE.
bool HasDSP, HasDSPR2;
// IsAndroid -- target is android
bool IsAndroid;
InstrItineraryData InstrItins;
// The instance to the register info section object
@ -144,7 +141,6 @@ public:
bool inMicroMipsMode() const { return InMicroMipsMode; }
bool hasDSP() const { return HasDSP; }
bool hasDSPR2() const { return HasDSPR2; }
bool isAndroid() const { return IsAndroid; }
bool isLinux() const { return IsLinux; }
bool useSmallSection() const { return UseSmallSection; }

12
test/CodeGen/Mips/return-vector-float4.ll
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@ -1,12 +0,0 @@
; RUN: llc -march=mipsel -mattr=+android < %s | FileCheck %s
define <4 x float> @retvec4() nounwind readnone {
entry:
; CHECK: lwc1 $f0
; CHECK: lwc1 $f2
; CHECK: lwc1 $f1
; CHECK: lwc1 $f3
ret <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
}