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https://github.com/c64scene-ar/llvm-6502.git
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Fix Mips long branch pass.
This pass no longer requires that the global pointer value be saved to the stack or register since it uses bal instruction to compute branch distance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160601 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
b22c9289b0
commit
60287963c7
@ -1005,6 +1005,10 @@ def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
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def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
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def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
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let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1,
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hasDelaySlot = 1, Defs = [RA] in
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def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>;
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def JAL : JumpLink<0x03, "jal">;
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def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
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def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
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@ -73,9 +73,6 @@ namespace {
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void splitMBB(MachineBasicBlock *MBB);
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void initMBBInfo();
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int64_t computeOffset(const MachineInstr *Br);
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bool offsetFitsIntoField(const MachineInstr *Br);
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unsigned addLongBranch(MachineBasicBlock &MBB, Iter Pos,
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MachineBasicBlock *Tgt, DebugLoc DL, bool Nop);
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void replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL,
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MachineBasicBlock *MBBOpnd);
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void expandToLongBranch(MBBInfo &Info);
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@ -178,7 +175,9 @@ void MipsLongBranch::initMBBInfo() {
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ReverseIter Br = getNonDebugInstr(MBB->rbegin(), End);
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if ((Br != End) && !Br->isIndirectBranch() &&
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(Br->isConditionalBranch() || Br->isUnconditionalBranch()))
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(Br->isConditionalBranch() ||
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(Br->isUnconditionalBranch() &&
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TM.getRelocationModel() == Reloc::PIC_)))
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MBBInfos[I].Br = (++Br).base();
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}
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}
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@ -204,77 +203,6 @@ int64_t MipsLongBranch::computeOffset(const MachineInstr *Br) {
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return -Offset + 4;
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}
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// Insert the following sequence:
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// (pic or N64)
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// lw $at, global_reg_slot
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// lw $at, got($L1)($at)
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// addiu $at, $at, lo($L1)
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// jr $at
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// noop
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// (static and !N64)
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// lui $at, hi($L1)
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// addiu $at, $at, lo($L1)
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// jr $at
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// noop
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unsigned MipsLongBranch::addLongBranch(MachineBasicBlock &MBB, Iter Pos,
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MachineBasicBlock *Tgt, DebugLoc DL,
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bool Nop) {
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MF->getInfo<MipsFunctionInfo>()->setEmitNOAT();
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bool IsPIC = (TM.getRelocationModel() == Reloc::PIC_);
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unsigned ABI = TM.getSubtarget<MipsSubtarget>().getTargetABI();
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bool N64 = (ABI == MipsSubtarget::N64);
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unsigned NumInstrs;
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if (IsPIC || N64) {
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bool HasMips64 = TM.getSubtarget<MipsSubtarget>().hasMips64();
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unsigned AT = N64 ? Mips::AT_64 : Mips::AT;
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unsigned Load = N64 ? Mips::LD_P8 : Mips::LW;
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unsigned ADDiu = N64 ? Mips::DADDiu : Mips::ADDiu;
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unsigned JR = N64 ? Mips::JR64 : Mips::JR;
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unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
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unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
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const MipsRegisterInfo *MRI =
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static_cast<const MipsRegisterInfo*>(TM.getRegisterInfo());
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unsigned SP = MRI->getFrameRegister(*MF);
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unsigned GlobalRegFI = MF->getInfo<MipsFunctionInfo>()->getGlobalRegFI();
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int64_t Offset = MF->getFrameInfo()->getObjectOffset(GlobalRegFI);
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if (isInt<16>(Offset)) {
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BuildMI(MBB, Pos, DL, TII->get(Load), AT).addReg(SP).addImm(Offset);
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NumInstrs = 1;
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} else {
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unsigned ADDu = N64 ? Mips::DADDu : Mips::ADDu;
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MipsAnalyzeImmediate::Inst LastInst(0, 0);
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MF->getInfo<MipsFunctionInfo>()->setEmitNOAT();
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NumInstrs = Mips::loadImmediate(Offset, N64, *TII, MBB, Pos, DL, true,
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&LastInst) + 2;
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BuildMI(MBB, Pos, DL, TII->get(ADDu), AT).addReg(SP).addReg(AT);
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BuildMI(MBB, Pos, DL, TII->get(Load), AT).addReg(AT)
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.addImm(SignExtend64<16>(LastInst.ImmOpnd));
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}
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BuildMI(MBB, Pos, DL, TII->get(Load), AT).addReg(AT).addMBB(Tgt, GOTFlag);
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BuildMI(MBB, Pos, DL, TII->get(ADDiu), AT).addReg(AT).addMBB(Tgt, OFSTFlag);
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BuildMI(MBB, Pos, DL, TII->get(JR)).addReg(Mips::AT, RegState::Kill);
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NumInstrs += 3;
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} else {
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BuildMI(MBB, Pos, DL, TII->get(Mips::LUi), Mips::AT)
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.addMBB(Tgt, MipsII::MO_ABS_HI);
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BuildMI(MBB, Pos, DL, TII->get(Mips::ADDiu), Mips::AT)
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.addReg(Mips::AT).addMBB(Tgt, MipsII::MO_ABS_LO);
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BuildMI(MBB, Pos, DL, TII->get(Mips::JR)).addReg(Mips::AT, RegState::Kill);
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NumInstrs = 3;
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}
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if (Nop) {
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BuildMI(MBB, Pos, DL, TII->get(Mips::NOP))->setIsInsideBundle();
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++NumInstrs;
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}
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return NumInstrs;
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}
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// Replace Br with a branch which has the opposite condition code and a
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// MachineBasicBlock operand MBBOpnd.
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void MipsLongBranch::replaceBranch(MachineBasicBlock &MBB, Iter Br,
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@ -304,57 +232,138 @@ void MipsLongBranch::replaceBranch(MachineBasicBlock &MBB, Iter Br,
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void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
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I.HasLongBranch = true;
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MachineBasicBlock *MBB = I.Br->getParent(), *Tgt = getTargetMBB(*I.Br);
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bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
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unsigned ABI = TM.getSubtarget<MipsSubtarget>().getTargetABI();
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bool N64 = ABI == MipsSubtarget::N64;
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MachineBasicBlock::iterator Pos;
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MachineBasicBlock *MBB = I.Br->getParent(), *TgtMBB = getTargetMBB(*I.Br);
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DebugLoc DL = I.Br->getDebugLoc();
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const BasicBlock *BB = MBB->getBasicBlock();
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MachineFunction::iterator FallThroughMBB = ++MachineFunction::iterator(MBB);
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MachineBasicBlock *LongBrMBB = MF->CreateMachineBasicBlock(BB);
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if (I.Br->isUnconditionalBranch()) {
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// Unconditional branch before transformation:
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// b $tgt
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// delay-slot-instr
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MF->insert(FallThroughMBB, LongBrMBB);
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MBB->removeSuccessor(TgtMBB);
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MBB->addSuccessor(LongBrMBB);
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if (IsPIC) {
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// $longbr:
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// addiu $sp, $sp, -regsize * 2
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// sw $ra, 0($sp)
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// bal $baltgt
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// sw $a3, regsize($sp)
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// $baltgt:
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// lui $a3, %hi($baltgt)
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// lui $at, %hi($tgt)
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// addiu $a3, $a3, %lo($baltgt)
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// addiu $at, $at, %lo($tgt)
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// subu $at, $at, $a3
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// addu $at, $ra, $at
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//
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// after transformation:
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// delay-slot-instr
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// lw $at, global_reg_slot
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// lw $at, %got($tgt)($at)
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// addiu $at, $at, %lo($tgt)
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// jr $at
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// nop
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I.Size += (addLongBranch(*MBB, llvm::next(Iter(I.Br)), Tgt, DL, true)
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- 1) * 4;
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// if n64:
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// lui $a3, %highest($baltgt)
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// lui $ra, %highest($tgt)
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// addiu $a3, $a3, %higher($baltgt)
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// addiu $ra, $ra, %higher($tgt)
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// dsll $a3, $a3, 32
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// dsll $ra, $ra, 32
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// subu $at, $at, $a3
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// addu $at, $at, $ra
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//
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// lw $ra, 0($sp)
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// lw $a3, regsize($sp)
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// jr $at
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// addiu $sp, $sp, regsize * 2
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// $fallthrough:
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//
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MF->getInfo<MipsFunctionInfo>()->setEmitNOAT();
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MachineBasicBlock *BalTgtMBB = MF->CreateMachineBasicBlock(BB);
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MF->insert(FallThroughMBB, BalTgtMBB);
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LongBrMBB->addSuccessor(BalTgtMBB);
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BalTgtMBB->addSuccessor(TgtMBB);
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// Remove branch and clear InsideBundle bit of the next instruction.
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llvm::next(MachineBasicBlock::instr_iterator(I.Br))
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->setIsInsideBundle(false);
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I.Br->eraseFromParent();
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return;
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int RegSize = N64 ? 8 : 4;
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unsigned AT = N64 ? Mips::AT_64 : Mips::AT;
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unsigned A3 = N64 ? Mips::A3_64 : Mips::A3;
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unsigned SP = N64 ? Mips::SP_64 : Mips::SP;
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unsigned RA = N64 ? Mips::RA_64 : Mips::RA;
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unsigned Load = N64 ? Mips::LD_P8 : Mips::LW;
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unsigned Store = N64 ? Mips::SD_P8 : Mips::SW;
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unsigned LUi = N64 ? Mips::LUi64 : Mips::LUi;
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unsigned ADDiu = N64 ? Mips::DADDiu : Mips::ADDiu;
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unsigned ADDu = N64 ? Mips::DADDu : Mips::ADDu;
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unsigned SUBu = N64 ? Mips::SUBu : Mips::SUBu;
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unsigned JR = N64 ? Mips::JR64 : Mips::JR;
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Pos = LongBrMBB->begin();
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BuildMI(*LongBrMBB, Pos, DL, TII->get(ADDiu), SP).addReg(SP)
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.addImm(-RegSize * 2);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Store)).addReg(RA).addReg(SP)
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.addImm(0);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Store)).addReg(A3).addReg(SP)
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.addImm(RegSize)->setIsInsideBundle();
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Pos = BalTgtMBB->begin();
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(LUi), A3)
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.addMBB(BalTgtMBB, MipsII::MO_ABS_HI);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(LUi), AT)
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.addMBB(TgtMBB, MipsII::MO_ABS_HI);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(ADDiu), A3).addReg(A3)
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.addMBB(BalTgtMBB, MipsII::MO_ABS_LO);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(ADDiu), AT).addReg(AT)
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.addMBB(TgtMBB, MipsII::MO_ABS_LO);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(SUBu), AT).addReg(AT).addReg(A3);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(ADDu), AT).addReg(RA).addReg(AT);
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if (N64) {
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(LUi), A3)
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.addMBB(BalTgtMBB, MipsII::MO_HIGHEST);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(LUi), RA)
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.addMBB(TgtMBB, MipsII::MO_HIGHEST);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(ADDiu), A3).addReg(A3)
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.addMBB(BalTgtMBB, MipsII::MO_HIGHER);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(ADDiu), RA).addReg(RA)
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.addMBB(TgtMBB, MipsII::MO_HIGHER);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DSLL), A3).addReg(A3)
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.addImm(32);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DSLL), RA).addReg(RA)
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.addImm(32);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(SUBu), AT).addReg(AT).addReg(A3);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(ADDu), AT).addReg(AT).addReg(RA);
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I.Size += 4 * 8;
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}
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Load), RA).addReg(SP).addImm(0);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Load), A3).addReg(SP).addImm(RegSize);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(JR)).addReg(AT);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(ADDiu), SP).addReg(SP)
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.addImm(RegSize * 2)->setIsInsideBundle();
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I.Size += 4 * 14;
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} else {
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// $longbr:
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// j $tgt
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// nop
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// $fallthrough:
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//
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Pos = LongBrMBB->begin();
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LongBrMBB->addSuccessor(TgtMBB);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::J)).addMBB(TgtMBB);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::NOP))->setIsInsideBundle();
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I.Size += 4 * 2;
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}
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assert(I.Br->isConditionalBranch() && "Conditional branch expected.");
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// Conditional branch before transformation:
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// b cc, $tgt
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// delay-slot-instr
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// FallThrough:
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//
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// after transformation:
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// b !cc, FallThrough
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// delay-slot-instr
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// NewMBB:
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// lw $at, global_reg_slot
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// lw $at, %got($tgt)($at)
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// addiu $at, $at, %lo($tgt)
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// jr $at
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// noop
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// FallThrough:
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MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(MBB->getBasicBlock());
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MF->insert(llvm::next(MachineFunction::iterator(MBB)), NewMBB);
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MBB->removeSuccessor(Tgt);
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MBB->addSuccessor(NewMBB);
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NewMBB->addSuccessor(Tgt);
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I.Size += addLongBranch(*NewMBB, NewMBB->begin(), Tgt, DL, true) * 4;
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replaceBranch(*MBB, I.Br, DL, *MBB->succ_begin());
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if (I.Br->isUnconditionalBranch()) {
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// Change branch destination.
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assert(I.Br->getDesc().getNumOperands() == 1);
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I.Br->RemoveOperand(0);
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I.Br->addOperand(MachineOperand::CreateMBB(LongBrMBB));
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} else
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// Change branch destination and reverse condition.
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replaceBranch(*MBB, I.Br, DL, FallThroughMBB);
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}
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static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) {
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@ -380,7 +389,6 @@ bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
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MF = &F;
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initMBBInfo();
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bool IsPIC = (TM.getRelocationModel() == Reloc::PIC_);
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SmallVector<MBBInfo, 16>::iterator I, E = MBBInfos.end();
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bool EverMadeChange = false, MadeChange = true;
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@ -393,18 +401,11 @@ bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
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if (!I->Br || I->HasLongBranch)
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continue;
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if (!ForceLongBranch) {
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int64_t Offset = computeOffset(I->Br);
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if (!ForceLongBranch)
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// Check if offset fits into 16-bit immediate field of branches.
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if ((I->Br->isConditionalBranch() || IsPIC) && isInt<16>(Offset / 4))
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if (isInt<16>(computeOffset(I->Br) / 4))
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continue;
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// Check if offset fits into 26-bit immediate field of jumps (J).
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if (I->Br->isUnconditionalBranch() && !IsPIC && isInt<26>(Offset / 4))
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continue;
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}
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expandToLongBranch(*I);
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++LongBranches;
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EverMadeChange = MadeChange = true;
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@ -1,12 +1,14 @@
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; RUN: llc -march=mipsel -force-mips-long-branch < %s | FileCheck %s
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; RUN: llc -march=mipsel -force-mips-long-branch < %s | FileCheck %s -check-prefix=O32
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; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 -force-mips-long-branch < %s | FileCheck %s -check-prefix=N64
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@g0 = external global i32
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define void @foo1(i32 %s) nounwind {
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entry:
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; CHECK: lw $[[R0:[a-z0-9]+]], %got($BB0_3)(${{[a-z0-9]+}})
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; CHECK: addiu $[[R1:[a-z0-9]+]], $[[R0]], %lo($BB0_3)
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; CHECK: jr $[[R1]]
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; O32: bal
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; N64: bal
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; N64: highest
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; N64: higher
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%tobool = icmp eq i32 %s, 0
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br i1 %tobool, label %if.end, label %if.then
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