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Switch from bytes to bits for alignment.

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Also, change GPRC for PPC32 to align on 32-bit boundary instead of 64-bit


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15975 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-08-21 20:14:40 +00:00
parent ff0a6e6aac
commit 608034ec1a
2 changed files with 6 additions and 6 deletions
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6
lib/Target/PowerPC/PPC32RegisterInfo.td
View File

@ -15,7 +15,7 @@ include "PowerPCRegisterInfo.td"
/// Register classes /// Register classes
// Allocate volatiles first // Allocate volatiles first
// then nonvolatiles in reverse order since stmw/lmw save from rN to r31 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
def GPRC : RegisterClass<i32, 8, def GPRC : RegisterClass<i32, 32,
[R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
R16, R15, R14, R13, R31, R0, R1, LR]> R16, R15, R14, R13, R31, R0, R1, LR]>
@ -33,8 +33,8 @@ def GPRC : RegisterClass<i32, 8,
}]; }];
} }
def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7, def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>; F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
def CRRC : RegisterClass<i32, 4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>; def CRRC : RegisterClass<i32, 32, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;

6
lib/Target/PowerPC/PPC64RegisterInfo.td
View File

@ -15,7 +15,7 @@ include "PowerPCRegisterInfo.td"
/// Register classes /// Register classes
// Allocate volatiles first // Allocate volatiles first
// then nonvolatiles in reverse order since stmw/lmw save from rN to r31 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
def GPRC : RegisterClass<i64, 8, def GPRC : RegisterClass<i64, 64,
[R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
R16, R15, R14, R13, R31, R0, R1, LR]> R16, R15, R14, R13, R31, R0, R1, LR]>
@ -33,8 +33,8 @@ def GPRC : RegisterClass<i64, 8,
}]; }];
} }
def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7, def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>; F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
def CRRC : RegisterClass<i32, 4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>; def CRRC : RegisterClass<i32, 32, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;