diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 2a195835354..389f154837b 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -119,28 +119,19 @@ class FPIdxStore funct, string opstr, RegisterClass DRC, // Instructions that convert an FP value to 32-bit fixed point. multiclass FFR1_W_M funct, string opstr> { - def _S : FFR1; - def _D32 : FFR1, + def _D32 : FFR1, Requires<[NotFP64bit, HasStdEnc]>; - def _D64 : FFR1, + def _D64 : FFR1, Requires<[IsFP64bit, HasStdEnc]> { let DecoderNamespace = "Mips64"; } } -// Instructions that convert an FP value to 64-bit fixed point. -let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in -multiclass FFR1_L_M funct, string opstr> { - def _S : FFR1; - def _D64 : FFR1; -} - // FP-to-FP conversion instructions. multiclass FFR1P_M funct, string opstr, SDNode OpNode> { - def _S : FFR1P; - def _D32 : FFR1P, + def _D32 : FFR1P, Requires<[NotFP64bit, HasStdEnc]>; - def _D64 : FFR1P, + def _D64 : FFR1P, Requires<[IsFP64bit, HasStdEnc]> { let DecoderNamespace = "Mips64"; } @@ -174,41 +165,57 @@ class FNMADDSUB funct, bits<3> fmt, string opstr, string fmtstr, //===----------------------------------------------------------------------===// // Floating Point Instructions //===----------------------------------------------------------------------===// -defm ROUND_W : FFR1_W_M<0xc, "round">; -defm ROUND_L : FFR1_L_M<0x8, "round">; -defm TRUNC_W : FFR1_W_M<0xd, "trunc">; -defm TRUNC_L : FFR1_L_M<0x9, "trunc">; -defm CEIL_W : FFR1_W_M<0xe, "ceil">; -defm CEIL_L : FFR1_L_M<0xa, "ceil">; -defm FLOOR_W : FFR1_W_M<0xf, "floor">; -defm FLOOR_L : FFR1_L_M<0xb, "floor">; -defm CVT_W : FFR1_W_M<0x24, "cvt">, NeverHasSideEffects; -//defm CVT_L : FFR1_L_M<0x25, "cvt">; +def ROUND_W_S : FFR1<0xc, 16, "round.w.s", FGR32, FGR32>; +def TRUNC_W_S : FFR1<0xd, 16, "trunc.w.s", FGR32, FGR32>; +def CEIL_W_S : FFR1<0xe, 16, "ceil.w.s", FGR32, FGR32>; +def FLOOR_W_S : FFR1<0xf, 16, "floor.w.s", FGR32, FGR32>; +def CVT_W_S : FFR1<0x24, 16, "cvt.w.s", FGR32, FGR32>, NeverHasSideEffects; -def CVT_S_W : FFR1<0x20, 20, "cvt", "s.w", FGR32, FGR32>, NeverHasSideEffects; -def CVT_L_S : FFR1<0x25, 16, "cvt", "l.s", FGR64, FGR32>, NeverHasSideEffects; -def CVT_L_D64: FFR1<0x25, 17, "cvt", "l.d", FGR64, FGR64>, NeverHasSideEffects; +defm ROUND_W : FFR1_W_M<0xc, "round.w.d">; +defm TRUNC_W : FFR1_W_M<0xd, "trunc.w.d">; +defm CEIL_W : FFR1_W_M<0xe, "ceil.w.d">; +defm FLOOR_W : FFR1_W_M<0xf, "floor.w.d">; +defm CVT_W : FFR1_W_M<0x24, "cvt.w.d">, NeverHasSideEffects; + +let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { + def ROUND_L_S : FFR1<0x8, 16, "round.l.s", FGR64, FGR32>; + def ROUND_L_D64 : FFR1<0x8, 17, "round.l.d", FGR64, FGR64>; + def TRUNC_L_S : FFR1<0x9, 16, "trunc.l.s", FGR64, FGR32>; + def TRUNC_L_D64 : FFR1<0x9, 17, "trunc.l.d", FGR64, FGR64>; + def CEIL_L_S : FFR1<0xa, 16, "ceil.l.s", FGR64, FGR32>; + def CEIL_L_D64 : FFR1<0xa, 17, "ceil.l.d", FGR64, FGR64>; + def FLOOR_L_S : FFR1<0xb, 16, "floor.l.s", FGR64, FGR32>; + def FLOOR_L_D64 : FFR1<0xb, 17, "floor.l.d", FGR64, FGR64>; +} + +def CVT_S_W : FFR1<0x20, 20, "cvt.s.w", FGR32, FGR32>, NeverHasSideEffects; +def CVT_L_S : FFR1<0x25, 16, "cvt.l.s", FGR64, FGR32>, NeverHasSideEffects; +def CVT_L_D64: FFR1<0x25, 17, "cvt.l.d", FGR64, FGR64>, NeverHasSideEffects; let Predicates = [NotFP64bit, HasStdEnc], neverHasSideEffects = 1 in { - def CVT_S_D32 : FFR1<0x20, 17, "cvt", "s.d", FGR32, AFGR64>; - def CVT_D32_W : FFR1<0x21, 20, "cvt", "d.w", AFGR64, FGR32>; - def CVT_D32_S : FFR1<0x21, 16, "cvt", "d.s", AFGR64, FGR32>; + def CVT_S_D32 : FFR1<0x20, 17, "cvt.s.d", FGR32, AFGR64>; + def CVT_D32_W : FFR1<0x21, 20, "cvt.d.w", AFGR64, FGR32>; + def CVT_D32_S : FFR1<0x21, 16, "cvt.d.s", AFGR64, FGR32>; } let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64", neverHasSideEffects = 1 in { - def CVT_S_D64 : FFR1<0x20, 17, "cvt", "s.d", FGR32, FGR64>; - def CVT_S_L : FFR1<0x20, 21, "cvt", "s.l", FGR32, FGR64>; - def CVT_D64_W : FFR1<0x21, 20, "cvt", "d.w", FGR64, FGR32>; - def CVT_D64_S : FFR1<0x21, 16, "cvt", "d.s", FGR64, FGR32>; - def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>; + def CVT_S_D64 : FFR1<0x20, 17, "cvt.s.d", FGR32, FGR64>; + def CVT_S_L : FFR1<0x20, 21, "cvt.s.l", FGR32, FGR64>; + def CVT_D64_W : FFR1<0x21, 20, "cvt.d.w", FGR64, FGR32>; + def CVT_D64_S : FFR1<0x21, 16, "cvt.d.s", FGR64, FGR32>; + def CVT_D64_L : FFR1<0x21, 21, "cvt.d.l", FGR64, FGR64>; } let Predicates = [NoNaNsFPMath, HasStdEnc] in { - defm FABS : FFR1P_M<0x5, "abs", fabs>; - defm FNEG : FFR1P_M<0x7, "neg", fneg>; + def FABS_S : FFR1P<0x5, 16, "abs.s", FGR32, FGR32, fabs>; + def FNEG_S : FFR1P<0x7, 16, "neg.s", FGR32, FGR32, fneg>; + defm FABS : FFR1P_M<0x5, "abs.d", fabs>; + defm FNEG : FFR1P_M<0x7, "neg.d", fneg>; } -defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>; + +def FSQRT_S : FFR1P<0x4, 16, "sqrt.s", FGR32, FGR32, fsqrt>; +defm FSQRT : FFR1P_M<0x4, "sqrt.d", fsqrt>; // The odd-numbered registers are only referenced when doing loads, // stores, and moves between floating-point and integer registers. @@ -245,10 +252,10 @@ def DMTC1 : FFRGPR<0x05, (outs FGR64:$fs), (ins CPU64Regs:$rt), "dmtc1\t$rt, $fs", [(set FGR64:$fs, (bitconvert CPU64Regs:$rt))]>; -def FMOV_S : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>; -def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>, +def FMOV_S : FFR1<0x6, 16, "mov.s", FGR32, FGR32>; +def FMOV_D32 : FFR1<0x6, 17, "mov.d", AFGR64, AFGR64>, Requires<[NotFP64bit, HasStdEnc]>; -def FMOV_D64 : FFR1<0x6, 17, "mov", "d", FGR64, FGR64>, +def FMOV_D64 : FFR1<0x6, 17, "mov.d", FGR64, FGR64>, Requires<[IsFP64bit, HasStdEnc]> { let DecoderNamespace = "Mips64"; } diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index c3c12c1fea0..5c20a1e5867 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -317,18 +317,18 @@ class FFCMOV _fmt, bits<1> _tf, dag outs, dag ins, string asmstr, } // FP unary instructions without patterns. -class FFR1 funct, bits<5> fmt, string opstr, string fmtstr, - RegisterClass DstRC, RegisterClass SrcRC> : +class FFR1 funct, bits<5> fmt, string opstr, RegisterClass DstRC, + RegisterClass SrcRC> : FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs), - !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), []> { + !strconcat(opstr, "\t$fd, $fs"), []> { let ft = 0; } // FP unary instructions with patterns. -class FFR1P funct, bits<5> fmt, string opstr, string fmtstr, - RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> : +class FFR1P funct, bits<5> fmt, string opstr, RegisterClass DstRC, + RegisterClass SrcRC, SDNode OpNode> : FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs), - !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), + !strconcat(opstr, "\t$fd, $fs"), [(set DstRC:$fd, (OpNode SrcRC:$fs))]> { let ft = 0; }