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ARM NEON VTBL/VTBX assembly parsing and encoding.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-12-15 22:27:11 +00:00
parent b6ff6ec85e
commit 60d99a5278
5 changed files with 43 additions and 51 deletions
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22
lib/Target/ARM/ARMExpandPseudoInsts.cpp
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@ -61,7 +61,7 @@ namespace {
void ExpandVST(MachineBasicBlock::iterator &MBBI);
void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
unsigned Opc, bool IsExt, unsigned NumRegs);
unsigned Opc, bool IsExt);
void ExpandMOV32BitImm(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI);
};
@ -637,7 +637,7 @@ void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
/// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
/// register operands to real instructions with D register operands.
void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
unsigned Opc, bool IsExt, unsigned NumRegs) {
unsigned Opc, bool IsExt) {
MachineInstr &MI = *MBBI;
MachineBasicBlock &MBB = *MI.getParent();
@ -653,11 +653,7 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
unsigned D0, D1, D2, D3;
GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
MIB.addReg(D0).addReg(D1);
if (NumRegs > 2)
MIB.addReg(D2);
if (NumRegs > 3)
MIB.addReg(D3);
MIB.addReg(D0);
// Copy the other source register operand.
MIB.addOperand(MI.getOperand(OpIdx++));
@ -1325,12 +1321,12 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
ExpandLaneOp(MBBI);
return true;
case ARM::VTBL2Pseudo: ExpandVTBL(MBBI, ARM::VTBL2, false, 2); return true;
case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false, 3); return true;
case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false, 4); return true;
case ARM::VTBX2Pseudo: ExpandVTBL(MBBI, ARM::VTBX2, true, 2); return true;
case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true, 3); return true;
case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true, 4); return true;
case ARM::VTBL2Pseudo: ExpandVTBL(MBBI, ARM::VTBL2, false); return true;
case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
case ARM::VTBX2Pseudo: ExpandVTBL(MBBI, ARM::VTBX2, true); return true;
case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
}
return false;

26
lib/Target/ARM/ARMInstrNEON.td
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@ -5198,17 +5198,17 @@ def VTBL1
let hasExtraSrcRegAllocReq = 1 in {
def VTBL2
: N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
(ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
"vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
(ins VecListTwoD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
"vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
def VTBL3
: N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
(ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
"vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
(ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
"vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
def VTBL4
: N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
(ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
(ins VecListFourD:$Vn, DPR:$Vm),
NVTBLFrm, IIC_VTB4,
"vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
"vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
} // hasExtraSrcRegAllocReq = 1
def VTBL2Pseudo
@ -5228,18 +5228,18 @@ def VTBX1
let hasExtraSrcRegAllocReq = 1 in {
def VTBX2
: N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
(ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
"vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
(ins DPR:$orig, VecListTwoD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
"vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
def VTBX3
: N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
(ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
(ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
NVTBLFrm, IIC_VTBX3,
"vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
"vtbx", "8", "$Vd, $Vn, $Vm",
"$orig = $Vd", []>;
def VTBX4
: N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
"vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
: N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
(ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
"vtbx", "8", "$Vd, $Vn, $Vm",
"$orig = $Vd", []>;
} // hasExtraSrcRegAllocReq = 1

5
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -2644,7 +2644,6 @@ static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
unsigned op = fieldFromInstruction32(Insn, 6, 1);
unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
@ -2653,10 +2652,8 @@ static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail; // Writeback
}
for (unsigned i = 0; i < length; ++i) {
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;

24
test/MC/ARM/neon-table-encoding.s
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@ -1,22 +1,22 @@
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
vtbl.8 d16, {d17}, d16
@ vtbl.8 d16, {d16, d17}, d18
@ vtbl.8 d16, {d16, d17, d18}, d20
@ vtbl.8 d16, {d16, d17, d18, d19}, d20
vtbl.8 d16, {d16, d17}, d18
vtbl.8 d16, {d16, d17, d18}, d20
vtbl.8 d16, {d16, d17, d18, d19}, d20
@ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xf3]
@ FIXME: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xf3]
@ FIXME: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xf3]
@ FIXME: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xf3]
@ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xf3]
@ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xf3]
@ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xf3]
vtbx.8 d18, {d16}, d17
@ vtbx.8 d19, {d16, d17}, d18
@ vtbx.8 d20, {d16, d17, d18}, d21
@ vtbx.8 d20, {d16, d17, d18, d19}, d21
vtbx.8 d19, {d16, d17}, d18
vtbx.8 d20, {d16, d17, d18}, d21
vtbx.8 d20, {d16, d17, d18, d19}, d21
@ CHECK: vtbx.8 d18, {d16}, d17 @ encoding: [0xe1,0x28,0xf0,0xf3]
@ FIXME: vtbx.8 d19, {d16, d17}, d18 @ encoding: [0xe2,0x39,0xf0,0xf3]
@ FIXME: vtbx.8 d20, {d16, d17, d18}, d21 @ encoding: [0xe5,0x4a,0xf0,0xf3]
@ FIXME: vtbx.8 d20, {d16, d17, d18, d19}, d21 @ encoding: [0xe5,0x4b,0xf0,0xf3]
@ CHECK: vtbx.8 d19, {d16, d17}, d18 @ encoding: [0xe2,0x39,0xf0,0xf3]
@ CHECK: vtbx.8 d20, {d16, d17, d18}, d21 @ encoding: [0xe5,0x4a,0xf0,0xf3]
@ CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 @ encoding: [0xe5,0x4b,0xf0,0xf3]

17
test/MC/ARM/neont2-table-encoding.s
View File

@ -1,5 +1,4 @@
@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
@ XFAIL: *
.code 16
@ -8,10 +7,10 @@
vtbl.8 d16, {d16, d17, d18}, d20
vtbl.8 d16, {d16, d17, d18, d19}, d20
@ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xff]
@ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xff]
@ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xff]
@ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xff]
@ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xf1,0xff,0xa0,0x08]
@ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xf0,0xff,0xa2,0x09]
@ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xf0,0xff,0xa4,0x0a]
@ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xf0,0xff,0xa4,0x0b]
vtbx.8 d18, {d16}, d17
@ -19,7 +18,7 @@
vtbx.8 d20, {d16, d17, d18}, d21
vtbx.8 d20, {d16, d17, d18, d19}, d21
@ CHECK: vtbx.8 d18, {d16}, d17 @ encoding: [0xe1,0x28,0xf0,0xff]
@ CHECK: vtbx.8 d19, {d16, d17}, d18 @ encoding: [0xe2,0x39,0xf0,0xff]
@ CHECK: vtbx.8 d20, {d16, d17, d18}, d21 @ encoding: [0xe5,0x4a,0xf0,0xff]
@ CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 @ encoding: [0xe5,0x4b,0xf0,0xff]
@ CHECK: vtbx.8 d18, {d16}, d17 @ encoding: [0xf0,0xff,0xe1,0x28]
@ CHECK: vtbx.8 d19, {d16, d17}, d18 @ encoding: [0xf0,0xff,0xe2,0x39]
@ CHECK: vtbx.8 d20, {d16, d17, d18}, d21 @ encoding: [0xf0,0xff,0xe5,0x4a]
@ CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 @ encoding: [0xf0,0xff,0xe5,0x4b]