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addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55531 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-08-29 07:40:52 +00:00
parent 3924f78a96
commit 612b79edc9
1 changed files with 10 additions and 3 deletions
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13
lib/Target/ARM/ARMInstrFormats.td
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@ -50,7 +50,6 @@ def ThumbFrm : Format<25>;
def VFPFrm : Format<26>;
//===----------------------------------------------------------------------===//
// ARM Instruction templates.
@ -59,6 +58,8 @@ def VFPFrm : Format<26>;
class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
Format f, string cstr>
: Instruction {
field bits<32> Inst;
let Namespace = "ARM";
bits<4> Opcode = opcod;
@ -122,11 +123,17 @@ class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern>;
asm, "", pattern> {
let Inst{5-6} = 0;
let Inst{7-10} = opcod;
}
class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern>;
asm, "", pattern> {
let Inst{5-6} = 0;
let Inst{7-10} = opcod;
}
class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,