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Use the correct LHS type when determining the legalization of a shift's RHS type.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127163 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-03-07 18:29:47 +00:00
parent a6428a401b
commit 6154f6c929
3 changed files with 21 additions and 18 deletions
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2
include/llvm/CodeGen/SelectionDAG.h
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@ -674,7 +674,7 @@ public:
/// getShiftAmountOperand - Return the specified value casted to /// getShiftAmountOperand - Return the specified value casted to
/// the target's desired shift amount type. /// the target's desired shift amount type.
SDValue getShiftAmountOperand(SDValue Op); SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op);
/// UpdateNodeOperands - *Mutate* the specified node in-place to have the /// UpdateNodeOperands - *Mutate* the specified node in-place to have the
/// specified operands. If the resultant node already exists in the DAG, /// specified operands. If the resultant node already exists in the DAG,

6
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -948,7 +948,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// Legalizing shifts/rotates requires adjusting the shift amount // Legalizing shifts/rotates requires adjusting the shift amount
// to the appropriate width. // to the appropriate width.
if (!Ops[1].getValueType().isVector()) if (!Ops[1].getValueType().isVector())
Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
Ops[1]));
break; break;
case ISD::SRL_PARTS: case ISD::SRL_PARTS:
case ISD::SRA_PARTS: case ISD::SRA_PARTS:
@ -956,7 +957,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// Legalizing shifts/rotates requires adjusting the shift amount // Legalizing shifts/rotates requires adjusting the shift amount
// to the appropriate width. // to the appropriate width.
if (!Ops[2].getValueType().isVector()) if (!Ops[2].getValueType().isVector())
Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2])); Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
Ops[2]));
break; break;
} }

7
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -1418,9 +1418,9 @@ SDValue SelectionDAG::getMDNode(const MDNode *MD) {
/// getShiftAmountOperand - Return the specified value casted to /// getShiftAmountOperand - Return the specified value casted to
/// the target's desired shift amount type. /// the target's desired shift amount type.
SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) { SDValue SelectionDAG::getShiftAmountOperand(EVT LHSTy, SDValue Op) {
EVT OpTy = Op.getValueType(); EVT OpTy = Op.getValueType();
MVT ShTy = TLI.getShiftAmountTy(OpTy); MVT ShTy = TLI.getShiftAmountTy(LHSTy);
if (OpTy == ShTy || OpTy.isVector()) return Op; if (OpTy == ShTy || OpTy.isVector()) return Op;
ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
@ -6314,7 +6314,8 @@ SDValue SelectionDAG::UnrollVectorOp(SDNode *N, unsigned ResNE) {
case ISD::ROTL: case ISD::ROTL:
case ISD::ROTR: case ISD::ROTR:
Scalars.push_back(getNode(N->getOpcode(), dl, EltVT, Operands[0], Scalars.push_back(getNode(N->getOpcode(), dl, EltVT, Operands[0],
getShiftAmountOperand(Operands[1]))); getShiftAmountOperand(Operands[0].getValueType(),
Operands[1])));
break; break;
case ISD::SIGN_EXTEND_INREG: case ISD::SIGN_EXTEND_INREG:
case ISD::FP_ROUND_INREG: { case ISD::FP_ROUND_INREG: {