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[mips] Align the stack to 16-bytes for mfp64.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193641 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2013-10-29 19:29:03 +00:00
parent 8b1d5e2052
commit 615a279f81
6 changed files with 25 additions and 4 deletions
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4
lib/Target/Mips/Mips.td
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@ -30,10 +30,12 @@ def MipsInstrInfo : InstrInfo;
// Mips Subtarget features // // Mips Subtarget features //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def StackAlign16 : SubtargetFeature<"stackalign16", "StackAlignment", "16",
"Set stack alignment to 16-bytes.">;
def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
"General Purpose Registers are 64-bit wide.">; "General Purpose Registers are 64-bit wide.">;
def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
"Support 64-bit FP registers.">; "Support 64-bit FP registers.", [StackAlign16]>;
def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
"true", "Only supports single precision float">; "true", "Only supports single precision float">;
def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",

2
lib/Target/Mips/Mips16FrameLowering.h
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@ -20,7 +20,7 @@ namespace llvm {
class Mips16FrameLowering : public MipsFrameLowering { class Mips16FrameLowering : public MipsFrameLowering {
public: public:
explicit Mips16FrameLowering(const MipsSubtarget &STI) explicit Mips16FrameLowering(const MipsSubtarget &STI)
: MipsFrameLowering(STI, 8) {} : MipsFrameLowering(STI, STI.stackAlignment()) {}
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function. /// the function.

2
lib/Target/Mips/MipsSEFrameLowering.h
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@ -21,7 +21,7 @@ namespace llvm {
class MipsSEFrameLowering : public MipsFrameLowering { class MipsSEFrameLowering : public MipsFrameLowering {
public: public:
explicit MipsSEFrameLowering(const MipsSubtarget &STI) explicit MipsSEFrameLowering(const MipsSubtarget &STI)
: MipsFrameLowering(STI, STI.hasMips64() ? 16 : 8) {} : MipsFrameLowering(STI, STI.stackAlignment()) {}
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function. /// the function.

2
lib/Target/Mips/MipsSubtarget.cpp
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@ -72,7 +72,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
RM(_RM), OverrideMode(NoOverride), TM(_TM) StackAlignment(8), RM(_RM), OverrideMode(NoOverride), TM(_TM)
{ {
std::string CPUName = CPU; std::string CPUName = CPU;
if (CPUName.empty()) if (CPUName.empty())

5
lib/Target/Mips/MipsSubtarget.h
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@ -116,6 +116,8 @@ protected:
// HasMSA -- supports MSA ASE. // HasMSA -- supports MSA ASE.
bool HasMSA; bool HasMSA;
unsigned StackAlignment;
InstrItineraryData InstrItins; InstrItineraryData InstrItins;
// The instance to the register info section object // The instance to the register info section object
@ -216,6 +218,9 @@ public:
// really use them if in addition we are in mips16 mode // really use them if in addition we are in mips16 mode
// //
static bool useConstantIslands(); static bool useConstantIslands();
unsigned stackAlignment() const { return StackAlignment; }
// Grab MipsRegInfo object // Grab MipsRegInfo object
const MipsReginfo &getMReginfo() const { return MRI; } const MipsReginfo &getMReginfo() const { return MRI; }

14
test/CodeGen/Mips/stack-alignment.ll Normal file
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@ -0,0 +1,14 @@
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck %s -check-prefix=32-FP64
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
; 32: addiu $sp, $sp, -8
; 32-FP64: addiu $sp, $sp, -16
; 64: addiu $sp, $sp, -16
define i32 @foo1() #0 {
entry:
ret i32 14
}
attributes #0 = { "no-frame-pointer-elim"="true" }