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https://github.com/c64scene-ar/llvm-6502.git
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mark some unsupported ops as unsupported
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24852 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -136,6 +136,17 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ , MVT::i32, Expand);
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setOperationAction(ISD::CTLZ , MVT::i32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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computeRegisterProperties();
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}
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@ -136,6 +136,17 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ , MVT::i32, Expand);
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setOperationAction(ISD::CTLZ , MVT::i32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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computeRegisterProperties();
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}
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