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Nuke PowerPCInstrFormats.h, its contents are dead. Remove the definitions
from the .td file that correspond to it git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23736 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -342,6 +342,13 @@ void PowerPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
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///
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///
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void PowerPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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void PowerPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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++EmittedInsts;
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++EmittedInsts;
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/// NOTE: THIS SHOULD NEVER BE CHECKED IN. STAY LOCAL IN CHRIS'S TREE.
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if (0 && MI->getOpcode() == PPC::OR)
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assert((MI->getOperand(0).getReg() != MI->getOperand(1).getReg() ||
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MI->getOperand(2).getReg() != MI->getOperand(1).getReg()) &&
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"noop copy emitted!");
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// Check for slwi/srwi mnemonics.
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// Check for slwi/srwi mnemonics.
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if (MI->getOpcode() == PPC::RLWINM) {
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if (MI->getOpcode() == PPC::RLWINM) {
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bool FoundMnemonic = false;
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bool FoundMnemonic = false;
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@ -18,7 +18,6 @@
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#define DEBUG_TYPE "bsel"
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#define DEBUG_TYPE "bsel"
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#include "PowerPC.h"
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#include "PowerPC.h"
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#include "PowerPCInstrBuilder.h"
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#include "PowerPCInstrBuilder.h"
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#include "PowerPCInstrInfo.h"
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#include "PPC32InstrInfo.h"
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#include "PPC32InstrInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Debug.h"
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@ -15,7 +15,7 @@
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#include "PowerPC.h"
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#include "PowerPC.h"
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#include "PowerPCInstrBuilder.h"
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#include "PowerPCInstrBuilder.h"
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#include "PowerPCInstrInfo.h"
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#include "PPC32InstrInfo.h"
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#include "PPC32TargetMachine.h"
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#include "PPC32TargetMachine.h"
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#include "PPC32ISelLowering.h"
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#include "PPC32ISelLowering.h"
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#include "llvm/Constants.h"
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#include "llvm/Constants.h"
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@ -10,34 +10,6 @@
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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class Format<bits<5> val> {
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bits<5> Value = val;
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}
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def Pseudo: Format<0>;
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def Gpr : Format<1>;
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def Gpr0 : Format<2>;
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def Simm16 : Format<3>;
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def PCRelimm24 : Format<5>;
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def Imm24 : Format<6>;
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def Imm5 : Format<7>;
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def PCRelimm14 : Format<8>;
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def Imm14 : Format<9>;
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def Imm2 : Format<10>;
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def Crf : Format<11>;
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def Imm3 : Format<12>;
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def Imm1 : Format<13>;
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def Fpr : Format<14>;
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def Imm4 : Format<15>;
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def Imm8 : Format<16>;
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def Disimm16 : Format<17>;
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def Disimm14 : Format<18>;
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def Spr : Format<19>;
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def Sgr : Format<20>;
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def Imm15 : Format<21>;
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def Vpr : Format<22>;
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def Imm6 : Format<23>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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//
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// PowerPC instruction formats
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// PowerPC instruction formats
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@ -14,7 +14,8 @@
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#ifndef POWERPC32_INSTRUCTIONINFO_H
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#ifndef POWERPC32_INSTRUCTIONINFO_H
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#define POWERPC32_INSTRUCTIONINFO_H
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#define POWERPC32_INSTRUCTIONINFO_H
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#include "PowerPCInstrInfo.h"
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#include "PowerPC.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "PPC32RegisterInfo.h"
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#include "PPC32RegisterInfo.h"
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namespace llvm {
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namespace llvm {
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@ -1,55 +0,0 @@
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//===- PowerPCInstrInfo.h - PowerPC Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef POWERPC_INSTRUCTIONINFO_H
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#define POWERPC_INSTRUCTIONINFO_H
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#include "PowerPC.h"
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#include "llvm/Target/TargetInstrInfo.h"
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namespace llvm {
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namespace PPCII {
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enum {
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VMX = 1 << 0,
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PPC64 = 1 << 1,
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};
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enum {
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None = 0,
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Gpr = 1,
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Gpr0 = 2,
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Simm16 = 3,
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Zimm16 = 4,
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PCRelimm24 = 5,
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Imm24 = 6,
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Imm5 = 7,
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PCRelimm14 = 8,
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Imm14 = 9,
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Imm2 = 10,
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Crf = 11,
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Imm3 = 12,
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Imm1 = 13,
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Fpr = 14,
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Imm4 = 15,
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Imm8 = 16,
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Disimm16 = 17,
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Disimm14 = 18,
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Spr = 19,
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Sgr = 20,
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Imm15 = 21,
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Vpr = 22
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};
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}
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}
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#endif
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