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[mips] Split IIIdiv int II_DIV, II_DIVU, II_DDIV, and II_DDIVU

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No functional change since the InstrItinData's were duplicated



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199497 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2014-01-17 14:48:06 +00:00
parent 235a81cbbf
commit 61a2eb1df5
4 changed files with 22 additions and 12 deletions
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4
lib/Target/Mips/MicroMipsInstrInfo.td
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@@ -110,9 +110,9 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
MULT_FM_MM<0x22c>; MULT_FM_MM<0x22c>;
def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>, def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
MULT_FM_MM<0x26c>; MULT_FM_MM<0x26c>;
def SDIV_MM : MMRel, Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
MULT_FM_MM<0x2ac>; MULT_FM_MM<0x2ac>;
def UDIV_MM : MMRel, Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
MULT_FM_MM<0x2ec>; MULT_FM_MM<0x2ec>;
/// Shift Instructions /// Shift Instructions

10
lib/Target/Mips/Mips64InstrInfo.td
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@@ -175,12 +175,14 @@ def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
II_DMULT>; II_DMULT>;
def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu, def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
II_DMULTU>; II_DMULTU>;
def DSDIV : Div<"ddiv", IIIdiv, GPR64Opnd, [HI0_64, LO0_64]>, MULT_FM<0, 0x1e>; def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
def DUDIV : Div<"ddivu", IIIdiv, GPR64Opnd, [HI0_64, LO0_64]>, MULT_FM<0, 0x1f>; MULT_FM<0, 0x1e>;
def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
MULT_FM<0, 0x1f>;
def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem, def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
IIIdiv, 0, 1, 1>; II_DDIV, 0, 1, 1>;
def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU, def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
IIIdiv, 0, 1, 1>; II_DDIVU, 0, 1, 1>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>; def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>;

8
lib/Target/Mips/MipsInstrInfo.td
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@@ -1074,9 +1074,9 @@ def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x18>; MULT_FM<0, 0x18>;
def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>, def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x19>; MULT_FM<0, 0x19>;
def SDIV : MMRel, Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x1a>; MULT_FM<0, 0x1a>;
def UDIV : MMRel, Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x1b>; MULT_FM<0, 0x1b>;
def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>; def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
@@ -1122,9 +1122,9 @@ def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>; def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
} }
def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv, def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
0, 1, 1>; 0, 1, 1>;
def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv, def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
0, 1, 1>; 0, 1, 1>;
def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;

12
lib/Target/Mips/MipsSchedule.td
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@@ -20,7 +20,6 @@ def IIAlu : InstrItinClass;
def IILoad : InstrItinClass; def IILoad : InstrItinClass;
def IIStore : InstrItinClass; def IIStore : InstrItinClass;
def IIBranch : InstrItinClass; def IIBranch : InstrItinClass;
def IIIdiv : InstrItinClass;
def IIslt : InstrItinClass; def IIslt : InstrItinClass;
def IIFcvt : InstrItinClass; def IIFcvt : InstrItinClass;
def IIFmove : InstrItinClass; def IIFmove : InstrItinClass;
@@ -47,6 +46,10 @@ def II_CLO : InstrItinClass;
def II_CLZ : InstrItinClass; def II_CLZ : InstrItinClass;
def II_DADDIU : InstrItinClass; def II_DADDIU : InstrItinClass;
def II_DADDU : InstrItinClass; def II_DADDU : InstrItinClass;
def II_DDIV : InstrItinClass;
def II_DDIVU : InstrItinClass;
def II_DIV : InstrItinClass;
def II_DIVU : InstrItinClass;
def II_DMULT : InstrItinClass; def II_DMULT : InstrItinClass;
def II_DMULTU : InstrItinClass; def II_DMULTU : InstrItinClass;
def II_DROTR : InstrItinClass; def II_DROTR : InstrItinClass;
@@ -151,7 +154,12 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
InstrItinData<II_MUL , [InstrStage<17, [IMULDIV]>]>, InstrItinData<II_MUL , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_MULT , [InstrStage<17, [IMULDIV]>]>, InstrItinData<II_MULT , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_MULTU , [InstrStage<17, [IMULDIV]>]>, InstrItinData<II_MULTU , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<IIIdiv , [InstrStage<38, [IMULDIV]>]>, InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_MSUBU , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_DIV , [InstrStage<38, [IMULDIV]>]>,
InstrItinData<II_DIVU , [InstrStage<38, [IMULDIV]>]>,
InstrItinData<II_DDIV , [InstrStage<38, [IMULDIV]>]>,
InstrItinData<II_DDIVU , [InstrStage<38, [IMULDIV]>]>,
InstrItinData<IIFcvt , [InstrStage<1, [ALU]>]>, InstrItinData<IIFcvt , [InstrStage<1, [ALU]>]>,
InstrItinData<IIFmove , [InstrStage<2, [ALU]>]>, InstrItinData<IIFmove , [InstrStage<2, [ALU]>]>,
InstrItinData<IIFcmp , [InstrStage<3, [ALU]>]>, InstrItinData<IIFcmp , [InstrStage<3, [ALU]>]>,