From 61a8a35f1693755a80e31f7760876ac91efcce99 Mon Sep 17 00:00:00 2001 From: Michael Kuperstein Date: Sun, 22 Dec 2013 07:51:53 +0000 Subject: [PATCH] Ensure bitcode encoding of calling conventions stays stable. Patch by Boaz Ouriel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197873 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/Bitcode/calling-conventions.3.2.ll | 150 +++++++++++++++++++++ test/Bitcode/calling-conventions.3.2.ll.bc | Bin 0 -> 1236 bytes 2 files changed, 150 insertions(+) create mode 100644 test/Bitcode/calling-conventions.3.2.ll create mode 100644 test/Bitcode/calling-conventions.3.2.ll.bc diff --git a/test/Bitcode/calling-conventions.3.2.ll b/test/Bitcode/calling-conventions.3.2.ll new file mode 100644 index 00000000000..aca9efd0892 --- /dev/null +++ b/test/Bitcode/calling-conventions.3.2.ll @@ -0,0 +1,150 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; calling-conventions.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not silently misread calling conventions of +; older bitcode files. + +declare ccc void @ccc() +; CHECK: declare void @ccc + +declare fastcc void @fastcc() +; CHECK: declare fastcc void @fastcc + +declare coldcc void @coldcc() +; CHECK: declare coldcc void @coldcc + +declare cc10 void @cc10() +; CHECK: declare cc10 void @cc10 + +declare spir_kernel void @spir_kernel() +; CHECK: declare spir_kernel void @spir_kernel + +declare spir_func void @spir_func() +; CHECK: declare spir_func void @spir_func + +declare intel_ocl_bicc void @intel_ocl_bicc() +; CHECK: declare intel_ocl_bicc void @intel_ocl_bicc + +declare x86_stdcallcc void @x86_stdcallcc() +; CHECK: declare x86_stdcallcc void @x86_stdcallcc + +declare x86_fastcallcc void @x86_fastcallcc() +; CHECK: declare x86_fastcallcc void @x86_fastcallcc + +declare x86_thiscallcc void @x86_thiscallcc() +; CHECK: declare x86_thiscallcc void @x86_thiscallcc + +declare arm_apcscc void @arm_apcscc() +; CHECK: declare arm_apcscc void @arm_apcscc + +declare arm_aapcscc void @arm_aapcscc() +; CHECK: declare arm_aapcscc void @arm_aapcscc + +declare arm_aapcs_vfpcc void @arm_aapcs_vfpcc() +; CHECK: declare arm_aapcs_vfpcc void @arm_aapcs_vfpcc + +declare msp430_intrcc void @msp430_intrcc() +; CHECK: declare msp430_intrcc void @msp430_intrcc + +declare ptx_kernel void @ptx_kernel() +; CHECK: declare ptx_kernel void @ptx_kernel + +declare ptx_device void @ptx_device() +; CHECK: declare ptx_device void @ptx_device + +define void @call_ccc() { +; CHECK: call void @ccc + call ccc void @ccc() + ret void +} + +define void @call_fastcc() { +; CHECK: call fastcc void @fastcc + call fastcc void @fastcc() + ret void +} + +define void @call_coldcc() { +; CHECK: call coldcc void @coldcc + call coldcc void @coldcc() + ret void +} + +define void @call_cc10 () { +; CHECK: call cc10 void @cc10 + call cc10 void @cc10 () + ret void +} + +define void @call_spir_kernel() { +; CHECK: call spir_kernel void @spir_kernel + call spir_kernel void @spir_kernel() + ret void +} + +define void @call_spir_func() { +; CHECK: call spir_func void @spir_func + call spir_func void @spir_func() + ret void +} + +define void @call_intel_ocl_bicc() { +; CHECK: call intel_ocl_bicc void @intel_ocl_bicc + call intel_ocl_bicc void @intel_ocl_bicc() + ret void +} + +define void @call_x86_stdcallcc() { +; CHECK: call x86_stdcallcc void @x86_stdcallcc + call x86_stdcallcc void @x86_stdcallcc() + ret void +} + +define void @call_x86_fastcallcc() { +; CHECK: call x86_fastcallcc void @x86_fastcallcc + call x86_fastcallcc void @x86_fastcallcc() + ret void +} + +define void @call_x86_thiscallcc() { +; CHECK: call x86_thiscallcc void @x86_thiscallcc + call x86_thiscallcc void @x86_thiscallcc() + ret void +} + +define void @call_arm_apcscc() { +; CHECK: call arm_apcscc void @arm_apcscc + call arm_apcscc void @arm_apcscc() + ret void +} + +define void @call_arm_aapcscc() { +; CHECK: call arm_aapcscc void @arm_aapcscc + call arm_aapcscc void @arm_aapcscc() + ret void +} + +define void @call_arm_aapcs_vfpcc() { +; CHECK: call arm_aapcs_vfpcc void @arm_aapcs_vfpcc + call arm_aapcs_vfpcc void @arm_aapcs_vfpcc() + ret void +} + +define void @call_msp430_intrcc() { +; CHECK: call msp430_intrcc void @msp430_intrcc + call msp430_intrcc void @msp430_intrcc() + ret void +} + +define void @call_ptx_kernel() { +; CHECK: call ptx_kernel void @ptx_kernel + call ptx_kernel void @ptx_kernel() + ret void +} + +define void @call_ptx_device() { +; CHECK: call ptx_device void @ptx_device + call ptx_device void @ptx_device() + ret void +} + diff --git a/test/Bitcode/calling-conventions.3.2.ll.bc b/test/Bitcode/calling-conventions.3.2.ll.bc new file mode 100644 index 0000000000000000000000000000000000000000..b3fad967db0e04778d63fcd3dda2a0e3777aea91 GIT binary patch literal 1236 zcmbu8PfXKL9LIm#I`%fIE3m*&hV3?t#wFr5bS7Iiw_-}fWEhQH2!$Bp#RHlcIVhzR zEHdSv2acc~IG8x};=zOglMq1@nK3&Vj0y2#f;uk-#Mcf7q(_@<@0-v2zVGk*mNgnn zePT!euMVJCq(Kh=rTAm&agCf=BpQk+@99yUMAjHlWi>I_E}(jSbhJ3iQeImC*&8fg z*3DUl8CUv(Kvpu>-KIsEYM+{ziY%<-NEo02%y{)WWkg@;Bg&X368`!kO%B^i8>K|C z#5Pi-3u**C#B4f*tpN5%h*L$1s^^qO0R2Zqr4~RfThh#^ikF>FqpHHTt9_~xn0sJR z<^oP*Y=yH&36+seL{nkJV@hQ>kShc}ECdD$fkGiLAFR|O&5}50ck!F6--^XOgF|m$u+QkqxR>7{XQ~U zJvZxkH(AwDYgBE$2bT?@#aJj|2;q!Q8lV-gCr41~`Gy$J9G+Ii3sU4M89YnJk$5Sf zPkLr@^!wKMeg41@hE{gj8Wi2As1}L5abSDP`o`C?6}c!!#(R4GWz!oEk{dcFy2+Sv za>cW)6+cc!V!a2ab?dk>+P>h1r5~-Y{!|El>_MW#zhmnPV%wIlWhTn*o3zzz^rE!GL7AfNlB|i-*7bo%-3w0vAjz;P1oE~2shG?_c8OQa)m_ty^ zU4HFC<-85wLSzE?3P$=o-W7S$y34RO5zPEL#(tm%YZOnWhf_TGr-wEgz<}2>Vpg67 z;03JP=-n)GNcpSnWn8tE#T{C*p=HUm^5*RAH!Nw{IICq7 TgqBUEB~9K-Ny}2K!j$JP{_!k4 literal 0 HcmV?d00001