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[mips][mips64r6] Add Relocations R_MIPS_PCHI16, R_MIPS_PCLO16

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Differential Revision: http://reviews.llvm.org/D3860


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209659 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic 2014-05-27 14:58:51 +00:00
parent 87d192bb72
commit 61e341e0bf
10 changed files with 56 additions and 0 deletions
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2
include/llvm/MC/MCExpr.h
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@ -262,6 +262,8 @@ public:
VK_Mips_GOT_LO16, VK_Mips_GOT_LO16,
VK_Mips_CALL_HI16, VK_Mips_CALL_HI16,
VK_Mips_CALL_LO16, VK_Mips_CALL_LO16,
VK_Mips_PCREL_HI16,
VK_Mips_PCREL_LO16,
VK_COFF_IMGREL32 // symbol@imgrel (image-relative) VK_COFF_IMGREL32 // symbol@imgrel (image-relative)
}; };

2
lib/MC/MCExpr.cpp
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@ -271,6 +271,8 @@ StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
case VK_Mips_GOT_LO16: return "GOT_LO16"; case VK_Mips_GOT_LO16: return "GOT_LO16";
case VK_Mips_CALL_HI16: return "CALL_HI16"; case VK_Mips_CALL_HI16: return "CALL_HI16";
case VK_Mips_CALL_LO16: return "CALL_LO16"; case VK_Mips_CALL_LO16: return "CALL_LO16";
case VK_Mips_PCREL_HI16: return "PCREL_HI16";
case VK_Mips_PCREL_LO16: return "PCREL_LO16";
case VK_COFF_IMGREL32: return "IMGREL32"; case VK_COFF_IMGREL32: return "IMGREL32";
} }
llvm_unreachable("Invalid variant kind"); llvm_unreachable("Invalid variant kind");

2
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@ -1982,6 +1982,8 @@ MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
.Case("call_lo", MCSymbolRefExpr::VK_Mips_CALL_LO16) .Case("call_lo", MCSymbolRefExpr::VK_Mips_CALL_LO16)
.Case("higher", MCSymbolRefExpr::VK_Mips_HIGHER) .Case("higher", MCSymbolRefExpr::VK_Mips_HIGHER)
.Case("highest", MCSymbolRefExpr::VK_Mips_HIGHEST) .Case("highest", MCSymbolRefExpr::VK_Mips_HIGHEST)
.Case("pcrel_hi", MCSymbolRefExpr::VK_Mips_PCREL_HI16)
.Case("pcrel_lo", MCSymbolRefExpr::VK_Mips_PCREL_LO16)
.Default(MCSymbolRefExpr::VK_None); .Default(MCSymbolRefExpr::VK_None);
assert(VK != MCSymbolRefExpr::VK_None); assert(VK != MCSymbolRefExpr::VK_None);

2
lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
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@ -166,6 +166,8 @@ static void printExpr(const MCExpr *Expr, raw_ostream &OS) {
case MCSymbolRefExpr::VK_Mips_GOT_LO16: OS << "%got_lo("; break; case MCSymbolRefExpr::VK_Mips_GOT_LO16: OS << "%got_lo("; break;
case MCSymbolRefExpr::VK_Mips_CALL_HI16: OS << "%call_hi("; break; case MCSymbolRefExpr::VK_Mips_CALL_HI16: OS << "%call_hi("; break;
case MCSymbolRefExpr::VK_Mips_CALL_LO16: OS << "%call_lo("; break; case MCSymbolRefExpr::VK_Mips_CALL_LO16: OS << "%call_lo("; break;
case MCSymbolRefExpr::VK_Mips_PCREL_HI16: OS << "%pcrel_hi("; break;
case MCSymbolRefExpr::VK_Mips_PCREL_LO16: OS << "%pcrel_lo("; break;
} }
OS << SRE->getSymbol(); OS << SRE->getSymbol();

6
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
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@ -56,6 +56,7 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
case Mips::fixup_MICROMIPS_GOT_PAGE: case Mips::fixup_MICROMIPS_GOT_PAGE:
case Mips::fixup_MICROMIPS_GOT_OFST: case Mips::fixup_MICROMIPS_GOT_OFST:
case Mips::fixup_MICROMIPS_GOT_DISP: case Mips::fixup_MICROMIPS_GOT_DISP:
case Mips::fixup_MIPS_PCLO16:
break; break;
case Mips::fixup_Mips_PC16: case Mips::fixup_Mips_PC16:
// So far we are only using this type for branches. // So far we are only using this type for branches.
@ -80,6 +81,7 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
case Mips::fixup_Mips_GOT_HI16: case Mips::fixup_Mips_GOT_HI16:
case Mips::fixup_Mips_CALL_HI16: case Mips::fixup_Mips_CALL_HI16:
case Mips::fixup_MICROMIPS_HI16: case Mips::fixup_MICROMIPS_HI16:
case Mips::fixup_MIPS_PCHI16:
// Get the 2nd 16-bits. Also add 1 if bit 15 is 1. // Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
Value = ((Value + 0x8000) >> 16) & 0xffff; Value = ((Value + 0x8000) >> 16) & 0xffff;
break; break;
@ -247,6 +249,8 @@ getFixupKindInfo(MCFixupKind Kind) const {
{ "fixup_Mips_CALL_LO16", 0, 16, 0 }, { "fixup_Mips_CALL_LO16", 0, 16, 0 },
{ "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_26_S1", 0, 26, 0 }, { "fixup_MICROMIPS_26_S1", 0, 26, 0 },
{ "fixup_MICROMIPS_HI16", 0, 16, 0 }, { "fixup_MICROMIPS_HI16", 0, 16, 0 },
{ "fixup_MICROMIPS_LO16", 0, 16, 0 }, { "fixup_MICROMIPS_LO16", 0, 16, 0 },
@ -306,6 +310,8 @@ getFixupKindInfo(MCFixupKind Kind) const {
{ "fixup_Mips_CALL_LO16", 16, 16, 0 }, { "fixup_Mips_CALL_LO16", 16, 16, 0 },
{ "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_26_S1", 6, 26, 0 }, { "fixup_MICROMIPS_26_S1", 6, 26, 0 },
{ "fixup_MICROMIPS_HI16", 16, 16, 0 }, { "fixup_MICROMIPS_HI16", 16, 16, 0 },
{ "fixup_MICROMIPS_LO16", 16, 16, 0 }, { "fixup_MICROMIPS_LO16", 16, 16, 0 },

6
lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
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@ -199,6 +199,12 @@ unsigned MipsELFObjectWriter::GetRelocType(const MCValue &Target,
case Mips::fixup_MIPS_PC26_S2: case Mips::fixup_MIPS_PC26_S2:
Type = ELF::R_MIPS_PC26_S2; Type = ELF::R_MIPS_PC26_S2;
break; break;
case Mips::fixup_MIPS_PCHI16:
Type = ELF::R_MIPS_PCHI16;
break;
case Mips::fixup_MIPS_PCLO16:
Type = ELF::R_MIPS_PCLO16;
break;
} }
return Type; return Type;
} }

6
lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
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@ -134,6 +134,12 @@ namespace Mips {
// resulting in - R_MIPS_PC26_S2 // resulting in - R_MIPS_PC26_S2
fixup_MIPS_PC26_S2, fixup_MIPS_PC26_S2,
// resulting in - R_MIPS_PCHI16
fixup_MIPS_PCHI16,
// resulting in - R_MIPS_PCLO16
fixup_MIPS_PCLO16,
// resulting in - R_MICROMIPS_26_S1 // resulting in - R_MICROMIPS_26_S1
fixup_MICROMIPS_26_S1, fixup_MICROMIPS_26_S1,

6
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
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@ -480,6 +480,12 @@ getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups,
case MCSymbolRefExpr::VK_Mips_CALL_LO16: case MCSymbolRefExpr::VK_Mips_CALL_LO16:
FixupKind = Mips::fixup_Mips_CALL_LO16; FixupKind = Mips::fixup_Mips_CALL_LO16;
break; break;
case MCSymbolRefExpr::VK_Mips_PCREL_HI16:
FixupKind = Mips::fixup_MIPS_PCHI16;
break;
case MCSymbolRefExpr::VK_Mips_PCREL_LO16:
FixupKind = Mips::fixup_MIPS_PCLO16;
break;
} // switch } // switch
Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind))); Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));

12
test/MC/Mips/mips32r6/relocations.s
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@ -23,6 +23,14 @@
# CHECK-FIXUP: bc bar # encoding: [0b110010AA,A,A,A] # CHECK-FIXUP: bc bar # encoding: [0b110010AA,A,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2 # CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2
# CHECK-FIXUP: aluipc $2, %pcrel_hi(bar) # encoding: [0xec,0x5f,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar@PCREL_HI16,
# CHECK-FIXUP: kind: fixup_MIPS_PCHI16
# CHECK-FIXUP: addiu $2, $2, %pcrel_lo(bar) # encoding: [0x24,0x42,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar@PCREL_LO16,
# CHECK-FIXUP: kind: fixup_MIPS_PCLO16
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Check that the appropriate relocations were created. # Check that the appropriate relocations were created.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
@ -33,6 +41,8 @@
# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0 # CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0
# CHECK-ELF: 0x10 R_MIPS_PC26_S2 bar 0x0 # CHECK-ELF: 0x10 R_MIPS_PC26_S2 bar 0x0
# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0 # CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0
# CHECK-ELF: 0x18 R_MIPS_PCHI16 bar 0x0
# CHECK-ELF: 0x1C R_MIPS_PCLO16 bar 0x0
# CHECK-ELF: ] # CHECK-ELF: ]
beqc $5, $6, bar beqc $5, $6, bar
@ -41,3 +51,5 @@
bnezc $9, bar bnezc $9, bar
balc bar balc bar
bc bar bc bar
aluipc $2, %pcrel_hi(bar)
addiu $2, $2, %pcrel_lo(bar)

12
test/MC/Mips/mips64r6/relocations.s
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@ -23,6 +23,14 @@
# CHECK-FIXUP: bc bar # encoding: [0b110010AA,A,A,A] # CHECK-FIXUP: bc bar # encoding: [0b110010AA,A,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2 # CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2
# CHECK-FIXUP: aluipc $2, %pcrel_hi(bar) # encoding: [0xec,0x5f,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar@PCREL_HI16,
# CHECK-FIXUP: kind: fixup_MIPS_PCHI16
# CHECK-FIXUP: addiu $2, $2, %pcrel_lo(bar) # encoding: [0x24,0x42,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar@PCREL_LO16,
# CHECK-FIXUP: kind: fixup_MIPS_PCLO16
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Check that the appropriate relocations were created. # Check that the appropriate relocations were created.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
@ -33,6 +41,8 @@
# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0 # CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0
# CHECK-ELF: 0x10 R_MIPS_PC26_S2 bar 0x0 # CHECK-ELF: 0x10 R_MIPS_PC26_S2 bar 0x0
# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0 # CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0
# CHECK-ELF: 0x18 R_MIPS_PCHI16 bar 0x0
# CHECK-ELF: 0x1C R_MIPS_PCLO16 bar 0x0
# CHECK-ELF: ] # CHECK-ELF: ]
beqc $5, $6, bar beqc $5, $6, bar
@ -41,3 +51,5 @@
bnezc $9, bar bnezc $9, bar
balc bar balc bar
bc bar bc bar
aluipc $2, %pcrel_hi(bar)
addiu $2, $2, %pcrel_lo(bar)