mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-12 07:37:34 +00:00
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
4984d647da
commit
6248a546f2
lib/Target/ARM
test/MC/ARM
utils/TableGen
@ -29,6 +29,16 @@ def nImmSplatI16 : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let ParserMatchClass = nImmSplatI16AsmOperand;
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}
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def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
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def nImmSplatI32 : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let ParserMatchClass = nImmSplatI32AsmOperand;
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}
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def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
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def nImmVMOVI32 : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let ParserMatchClass = nImmVMOVI32AsmOperand;
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}
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def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
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def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
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@ -3757,7 +3767,7 @@ def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
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}
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def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
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(outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
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(outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
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IIC_VMOVImm,
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"vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
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[(set DPR:$Vd,
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@ -3775,7 +3785,7 @@ def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
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}
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def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
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(outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
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(outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
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IIC_VMOVImm,
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"vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
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[(set QPR:$Vd,
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@ -3806,7 +3816,7 @@ def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
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}
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def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
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(outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
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(outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
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IIC_VMOVImm,
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"vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
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[(set DPR:$Vd,
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@ -3824,7 +3834,7 @@ def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
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}
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def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
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(outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
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(outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
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IIC_VMOVImm,
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"vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
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[(set QPR:$Vd,
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@ -3863,14 +3873,14 @@ def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
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}
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def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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(ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
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"vmvn", "i32", "$Vd, $SIMM", "",
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[(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
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let Inst{11-8} = SIMM{11-8};
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}
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def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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(ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
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"vmvn", "i32", "$Vd, $SIMM", "",
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[(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
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let Inst{11-8} = SIMM{11-8};
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@ -4348,14 +4358,14 @@ def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
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}
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def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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(ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
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"vmov", "i32", "$Vd, $SIMM", "",
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[(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
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let Inst{11-8} = SIMM{11-8};
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}
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def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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(ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
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"vmov", "i32", "$Vd, $SIMM", "",
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[(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
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let Inst{11-8} = SIMM{11-8};
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@ -935,6 +935,37 @@ public:
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return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
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}
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bool isNEONi32splat() const {
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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// Must be a constant.
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if (!CE) return false;
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int64_t Value = CE->getValue();
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// i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
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return (Value >= 0 && Value < 256) ||
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(Value >= 0x0100 && Value <= 0xff00) ||
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(Value >= 0x010000 && Value <= 0xff0000) ||
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(Value >= 0x01000000 && Value <= 0xff000000);
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}
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bool isNEONi32vmov() const {
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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// Must be a constant.
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if (!CE) return false;
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int64_t Value = CE->getValue();
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// i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
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// for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
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return (Value >= 0 && Value < 256) ||
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(Value >= 0x0100 && Value <= 0xff00) ||
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(Value >= 0x010000 && Value <= 0xff0000) ||
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(Value >= 0x01000000 && Value <= 0xff000000) ||
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(Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
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(Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
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}
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void addExpr(MCInst &Inst, const MCExpr *Expr) const {
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// Add as immediates when possible. Null MCExpr = 0.
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if (Expr == 0)
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@ -1477,6 +1508,34 @@ public:
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Inst.addOperand(MCOperand::CreateImm(Value));
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}
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void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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// The immediate encodes the type of constant as well as the value.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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unsigned Value = CE->getValue();
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if (Value >= 256 && Value <= 0xff00)
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Value = (Value >> 8) | 0x200;
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else if (Value > 0xffff && Value <= 0xff0000)
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Value = (Value >> 16) | 0x400;
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else if (Value > 0xffffff)
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Value = (Value >> 24) | 0x600;
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Inst.addOperand(MCOperand::CreateImm(Value));
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}
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void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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// The immediate encodes the type of constant as well as the value.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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unsigned Value = CE->getValue();
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if (Value >= 256 && Value <= 0xffff)
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Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
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else if (Value > 0xffff && Value <= 0xffffff)
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Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
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else if (Value > 0xffffff)
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Value = (Value >> 24) | 0x600;
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Inst.addOperand(MCOperand::CreateImm(Value));
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}
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virtual void print(raw_ostream &OS) const;
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static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
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@ -3,23 +3,23 @@
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vmov.i8 d16, #0x8
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vmov.i16 d16, #0x10
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vmov.i16 d16, #0x1000
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@ vmov.i32 d16, #0x20
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@ vmov.i32 d16, #0x2000
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@ vmov.i32 d16, #0x200000
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@ vmov.i32 d16, #0x20000000
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@ vmov.i32 d16, #0x20FF
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@ vmov.i32 d16, #0x20FFFF
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vmov.i32 d16, #0x20
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vmov.i32 d16, #0x2000
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vmov.i32 d16, #0x200000
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vmov.i32 d16, #0x20000000
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vmov.i32 d16, #0x20FF
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vmov.i32 d16, #0x20FFFF
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@ vmov.i64 d16, #0xFF0000FF0000FFFF
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@ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2]
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@ CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2]
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@ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2]
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@ FIXME: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2]
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@ FIXME: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2]
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@ FIXME: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2]
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@ FIXME: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2]
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@ FIXME: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2]
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@ FIXME: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2]
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@ CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2]
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@ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2]
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@ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2]
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@ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2]
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@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2]
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@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2]
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@ FIXME: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3]
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@ -27,42 +27,42 @@
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vmov.i8 q8, #0x8
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vmov.i16 q8, #0x10
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vmov.i16 q8, #0x1000
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@ vmov.i32 q8, #0x20
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@ vmov.i32 q8, #0x2000
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@ vmov.i32 q8, #0x200000
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@ vmov.i32 q8, #0x20000000
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@ vmov.i32 q8, #0x20FF
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@ vmov.i32 q8, #0x20FFFF
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vmov.i32 q8, #0x20
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vmov.i32 q8, #0x2000
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vmov.i32 q8, #0x200000
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vmov.i32 q8, #0x20000000
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vmov.i32 q8, #0x20FF
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vmov.i32 q8, #0x20FFFF
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@ vmov.i64 q8, #0xFF0000FF0000FFFF
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@ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2]
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@ CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2]
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@ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2]
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@ FIXME: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2]
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@ FIXME: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2]
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@ FIXME: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2]
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@ FIXME: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2]
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@ FIXME: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2]
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@ FIXME: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2]
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@ CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2]
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@ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2]
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@ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2]
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@ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2]
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@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2]
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@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2]
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@ FIXME: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3]
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vmvn.i16 d16, #0x10
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vmvn.i16 d16, #0x1000
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@ vmvn.i32 d16, #0x20
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@ vmvn.i32 d16, #0x2000
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@ vmvn.i32 d16, #0x200000
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@ vmvn.i32 d16, #0x20000000
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@ vmvn.i32 d16, #0x20FF
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@ vmvn.i32 d16, #0x20FFFF
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vmvn.i32 d16, #0x20
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vmvn.i32 d16, #0x2000
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vmvn.i32 d16, #0x200000
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vmvn.i32 d16, #0x20000000
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vmvn.i32 d16, #0x20FF
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vmvn.i32 d16, #0x20FFFF
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@ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2]
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@ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2]
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@ FIXME: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2]
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@ FIXME: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2]
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@ FIXME: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2]
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@ FIXME: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2]
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@ FIXME: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2]
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@ FIXME: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2]
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@ CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2]
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@ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2]
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@ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2]
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@ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2]
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@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2]
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@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2]
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vmovl.s8 q8, d16
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vmovl.s16 q8, d16
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@ -5,66 +5,66 @@
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vmov.i8 d16, #0x8
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vmov.i16 d16, #0x10
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vmov.i16 d16, #0x1000
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@ vmov.i32 d16, #0x20
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@ vmov.i32 d16, #0x2000
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@ vmov.i32 d16, #0x200000
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@ vmov.i32 d16, #0x20000000
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@ vmov.i32 d16, #0x20FF
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@ vmov.i32 d16, #0x20FFFF
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vmov.i32 d16, #0x20
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vmov.i32 d16, #0x2000
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vmov.i32 d16, #0x200000
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vmov.i32 d16, #0x20000000
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vmov.i32 d16, #0x20FF
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vmov.i32 d16, #0x20FFFF
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@ vmov.i64 d16, #0xFF0000FF0000FFFF
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@ CHECK: vmov.i8 d16, #0x8 @ encoding: [0xc0,0xef,0x18,0x0e]
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@ CHECK: vmov.i16 d16, #0x10 @ encoding: [0xc1,0xef,0x10,0x08]
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@ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0xc1,0xef,0x10,0x0a]
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@ FIXME: vmov.i32 d16, #0x20 @ encoding: [0xc2,0xef,0x10,0x00]
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@ FIXME: vmov.i32 d16, #0x2000 @ encoding: [0xc2,0xef,0x10,0x02]
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@ FIXME: vmov.i32 d16, #0x200000 @ encoding: [0xc2,0xef,0x10,0x04]
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@ FIXME: vmov.i32 d16, #0x20000000 @ encoding: [0xc2,0xef,0x10,0x06]
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@ FIXME: vmov.i32 d16, #0x20FF @ encoding: [0xc2,0xef,0x10,0x0c]
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@ FIXME: vmov.i32 d16, #0x20FFFF @ encoding: [0xc2,0xef,0x10,0x0d]
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@ CHECK: vmov.i32 d16, #0x20 @ encoding: [0xc2,0xef,0x10,0x00]
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@ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0xc2,0xef,0x10,0x02]
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@ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0xc2,0xef,0x10,0x04]
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||||
@ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0xc2,0xef,0x10,0x06]
|
||||
@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0xc2,0xef,0x10,0x0c]
|
||||
@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0xc2,0xef,0x10,0x0d]
|
||||
@ FIXME: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0xc1,0xff,0x33,0x0e]
|
||||
|
||||
|
||||
vmov.i8 q8, #0x8
|
||||
vmov.i16 q8, #0x10
|
||||
vmov.i16 q8, #0x1000
|
||||
@ vmov.i32 q8, #0x20
|
||||
@ vmov.i32 q8, #0x2000
|
||||
@ vmov.i32 q8, #0x200000
|
||||
@ vmov.i32 q8, #0x20000000
|
||||
@ vmov.i32 q8, #0x20FF
|
||||
@ vmov.i32 q8, #0x20FFFF
|
||||
vmov.i32 q8, #0x20
|
||||
vmov.i32 q8, #0x2000
|
||||
vmov.i32 q8, #0x200000
|
||||
vmov.i32 q8, #0x20000000
|
||||
vmov.i32 q8, #0x20FF
|
||||
vmov.i32 q8, #0x20FFFF
|
||||
@ vmov.i64 q8, #0xFF0000FF0000FFFF
|
||||
|
||||
@ CHECK: vmov.i8 q8, #0x8 @ encoding: [0xc0,0xef,0x58,0x0e]
|
||||
@ CHECK: vmov.i16 q8, #0x10 @ encoding: [0xc1,0xef,0x50,0x08]
|
||||
@ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0xc1,0xef,0x50,0x0a]
|
||||
@ FIXME: vmov.i32 q8, #0x20 @ encoding: [0xc2,0xef,0x50,0x00]
|
||||
@ FIXME: vmov.i32 q8, #0x2000 @ encoding: [0xc2,0xef,0x50,0x02]
|
||||
@ FIXME: vmov.i32 q8, #0x200000 @ encoding: [0xc2,0xef,0x50,0x04]
|
||||
@ FIXME: vmov.i32 q8, #0x20000000 @ encoding: [0xc2,0xef,0x50,0x06]
|
||||
@ FIXME: vmov.i32 q8, #0x20FF @ encoding: [0xc2,0xef,0x50,0x0c]
|
||||
@ FIXME: vmov.i32 q8, #0x20FFFF @ encoding: [0xc2,0xef,0x50,0x0d]
|
||||
@ CHECK: vmov.i32 q8, #0x20 @ encoding: [0xc2,0xef,0x50,0x00]
|
||||
@ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0xc2,0xef,0x50,0x02]
|
||||
@ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0xc2,0xef,0x50,0x04]
|
||||
@ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0xc2,0xef,0x50,0x06]
|
||||
@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0xc2,0xef,0x50,0x0c]
|
||||
@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0xc2,0xef,0x50,0x0d]
|
||||
@ FIXME: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0xc1,0xff,0x73,0x0e]
|
||||
|
||||
|
||||
vmvn.i16 d16, #0x10
|
||||
vmvn.i16 d16, #0x1000
|
||||
@ vmvn.i32 d16, #0x20
|
||||
@ vmvn.i32 d16, #0x2000
|
||||
@ vmvn.i32 d16, #0x200000
|
||||
@ vmvn.i32 d16, #0x20000000
|
||||
@ vmvn.i32 d16, #0x20FF
|
||||
@ vmvn.i32 d16, #0x20FFFF
|
||||
vmvn.i32 d16, #0x20
|
||||
vmvn.i32 d16, #0x2000
|
||||
vmvn.i32 d16, #0x200000
|
||||
vmvn.i32 d16, #0x20000000
|
||||
vmvn.i32 d16, #0x20FF
|
||||
vmvn.i32 d16, #0x20FFFF
|
||||
|
||||
@ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0xc1,0xef,0x30,0x08]
|
||||
@ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0xc1,0xef,0x30,0x0a]
|
||||
@ FIXME: vmvn.i32 d16, #0x20 @ encoding: [0xc2,0xef,0x30,0x00]
|
||||
@ FIXME: vmvn.i32 d16, #0x2000 @ encoding: [0xc2,0xef,0x30,0x02]
|
||||
@ FIXME: vmvn.i32 d16, #0x200000 @ encoding: [0xc2,0xef,0x30,0x04]
|
||||
@ FIXME: vmvn.i32 d16, #0x20000000 @ encoding: [0xc2,0xef,0x30,0x06]
|
||||
@ FIXME: vmvn.i32 d16, #0x20FF @ encoding: [0xc2,0xef,0x30,0x0c]
|
||||
@ FIXME: vmvn.i32 d16, #0x20FFFF @ encoding: [0xc2,0xef,0x30,0x0d]
|
||||
@ CHECK: vmvn.i32 d16, #0x20 @ encoding: [0xc2,0xef,0x30,0x00]
|
||||
@ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0xc2,0xef,0x30,0x02]
|
||||
@ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0xc2,0xef,0x30,0x04]
|
||||
@ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0xc2,0xef,0x30,0x06]
|
||||
@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0xc2,0xef,0x30,0x0c]
|
||||
@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0xc2,0xef,0x30,0x0d]
|
||||
|
||||
|
||||
vmovl.s8 q8, d16
|
||||
|
||||
@ -599,6 +599,8 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
|
||||
IMM("nModImm");
|
||||
IMM("nImmSplatI8");
|
||||
IMM("nImmSplatI16");
|
||||
IMM("nImmSplatI32");
|
||||
IMM("nImmVMOVI32");
|
||||
IMM("imm0_7");
|
||||
IMM("imm0_15");
|
||||
IMM("imm0_255");
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user