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Avoid sinking machine instructions into a loop.
MachineLoopInfo is already available when MachineSinking runs, so the check is free. There is no test case because it would require a critical edge into a loop, and CodeGenPrepare splits those. This check is just to be extra careful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101420 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -20,6 +20,7 @@
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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@ -37,6 +38,7 @@ namespace {
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const TargetRegisterInfo *TRI;
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MachineRegisterInfo *RegInfo; // Machine register information
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MachineDominatorTree *DT; // Machine dominator tree
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MachineLoopInfo *LI;
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AliasAnalysis *AA;
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BitVector AllocatableSet; // Which physregs are allocatable?
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@ -51,7 +53,9 @@ namespace {
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MachineFunctionPass::getAnalysisUsage(AU);
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AU.addRequired<AliasAnalysis>();
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addPreserved<MachineLoopInfo>();
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}
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private:
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bool ProcessBlock(MachineBasicBlock &MBB);
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@ -102,6 +106,7 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
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TRI = TM.getRegisterInfo();
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RegInfo = &MF.getRegInfo();
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DT = &getAnalysis<MachineDominatorTree>();
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LI = &getAnalysis<MachineLoopInfo>();
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AA = &getAnalysis<AliasAnalysis>();
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AllocatableSet = TRI->getAllocatableSet(MF);
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@ -291,6 +296,12 @@ bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) {
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return false;
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}
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// Don't sink instructions into a loop.
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if (LI->isLoopHeader(SuccToSinkTo)) {
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DEBUG(dbgs() << " *** PUNTING: Loop header found\n");
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return false;
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}
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// Otherwise we are OK with sinking along a critical edge.
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DEBUG(dbgs() << "Sinking along critical edge.\n");
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}
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