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Replace copyRegToReg with copyPhysReg for Blackfin.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108077 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-07-11 05:44:34 +00:00
parent 4ea8771535
commit 629d80742a
2 changed files with 64 additions and 62 deletions
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116
lib/Target/Blackfin/BlackfinInstrInfo.cpp
View File

@ -122,6 +122,66 @@ InsertBranch(MachineBasicBlock &MBB,
llvm_unreachable("Implement conditional branches!");
}
void BlackfinInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const {
if (BF::ALLRegClass.contains(DestReg, SrcReg)) {
BuildMI(MBB, I, DL, get(BF::MOVE), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
return;
}
if (BF::D16RegClass.contains(DestReg, SrcReg)) {
BuildMI(MBB, I, DL, get(BF::SLL16i), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc))
.addImm(0);
return;
}
if (BF::DRegClass.contains(DestReg)) {
if (SrcReg == BF::NCC) {
BuildMI(MBB, I, DL, get(BF::MOVENCC_z), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
BuildMI(MBB, I, DL, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0);
return;
}
if (SrcReg == BF::CC) {
BuildMI(MBB, I, DL, get(BF::MOVECC_zext), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
return;
}
}
if (BF::DRegClass.contains(SrcReg)) {
if (DestReg == BF::NCC) {
BuildMI(MBB, I, DL, get(BF::SETEQri_not), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc)).addImm(0);
return;
}
if (DestReg == BF::CC) {
BuildMI(MBB, I, DL, get(BF::MOVECC_nz), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
return;
}
}
if (DestReg == BF::NCC && SrcReg == BF::CC) {
BuildMI(MBB, I, DL, get(BF::MOVE_ncccc), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
return;
}
if (DestReg == BF::CC && SrcReg == BF::NCC) {
BuildMI(MBB, I, DL, get(BF::MOVE_ccncc), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
return;
}
llvm_unreachable("Bad reg-to-reg copy");
}
static bool inClass(const TargetRegisterClass &Test,
unsigned Reg,
const TargetRegisterClass *RC) {
@ -131,62 +191,6 @@ static bool inClass(const TargetRegisterClass &Test,
return &Test==RC || Test.hasSubClass(RC);
}
bool BlackfinInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg,
unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC,
DebugLoc DL) const {
if (inClass(BF::ALLRegClass, DestReg, DestRC) &&
inClass(BF::ALLRegClass, SrcReg, SrcRC)) {
BuildMI(MBB, I, DL, get(BF::MOVE), DestReg).addReg(SrcReg);
return true;
}
if (inClass(BF::D16RegClass, DestReg, DestRC) &&
inClass(BF::D16RegClass, SrcReg, SrcRC)) {
BuildMI(MBB, I, DL, get(BF::SLL16i), DestReg).addReg(SrcReg).addImm(0);
return true;
}
if (inClass(BF::AnyCCRegClass, SrcReg, SrcRC) &&
inClass(BF::DRegClass, DestReg, DestRC)) {
if (inClass(BF::NotCCRegClass, SrcReg, SrcRC)) {
BuildMI(MBB, I, DL, get(BF::MOVENCC_z), DestReg).addReg(SrcReg);
BuildMI(MBB, I, DL, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0);
} else {
BuildMI(MBB, I, DL, get(BF::MOVECC_zext), DestReg).addReg(SrcReg);
}
return true;
}
if (inClass(BF::AnyCCRegClass, DestReg, DestRC) &&
inClass(BF::DRegClass, SrcReg, SrcRC)) {
if (inClass(BF::NotCCRegClass, DestReg, DestRC))
BuildMI(MBB, I, DL, get(BF::SETEQri_not), DestReg).addReg(SrcReg);
else
BuildMI(MBB, I, DL, get(BF::MOVECC_nz), DestReg).addReg(SrcReg);
return true;
}
if (inClass(BF::NotCCRegClass, DestReg, DestRC) &&
inClass(BF::JustCCRegClass, SrcReg, SrcRC)) {
BuildMI(MBB, I, DL, get(BF::MOVE_ncccc), DestReg).addReg(SrcReg);
return true;
}
if (inClass(BF::JustCCRegClass, DestReg, DestRC) &&
inClass(BF::NotCCRegClass, SrcReg, SrcRC)) {
BuildMI(MBB, I, DL, get(BF::MOVE_ccncc), DestReg).addReg(SrcReg);
return true;
}
llvm_unreachable((std::string("Bad regclasses for reg-to-reg copy: ")+
SrcRC->getName() + " -> " + DestRC->getName()).c_str());
return false;
}
void
BlackfinInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,

10
lib/Target/Blackfin/BlackfinInstrInfo.h
View File

@ -47,12 +47,10 @@ namespace llvm {
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC,
DebugLoc DL) const;
virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,