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Move load / store multiple before post-alloc scheduling.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83236 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-10-02 04:57:15 +00:00
parent 1ec8e194eb
commit 62a1b5db44
4 changed files with 7 additions and 17 deletions
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12
lib/Target/ARM/ARMTargetMachine.cpp
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@@ -22,10 +22,6 @@
#include "llvm/Target/TargetRegistry.h"
using namespace llvm;
static cl::opt<bool>
LdStBeforeSched("ldstopti-before-sched2", cl::Hidden,
cl::desc("Move ld / st multiple pass before postalloc scheduling"));
static const MCAsmInfo *createMCAsmInfo(const Target &T,
const StringRef &TT) {
Triple TheTriple(TT);
@@ -109,8 +105,7 @@ bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
if (LdStBeforeSched)
PM.add(createARMLoadStoreOptimizationPass());
PM.add(createARMLoadStoreOptimizationPass());
return true;
}
@@ -118,11 +113,8 @@ bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) {
if (!LdStBeforeSched)
PM.add(createARMLoadStoreOptimizationPass());
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
PM.add(createIfConverterPass());
}
if (Subtarget.isThumb2()) {
PM.add(createThumb2ITBlockPass());