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Move load / store multiple before post-alloc scheduling.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83236 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-10-02 04:57:15 +00:00
parent 1ec8e194eb
commit 62a1b5db44
4 changed files with 7 additions and 17 deletions
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12
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -22,10 +22,6 @@
#include "llvm/Target/TargetRegistry.h" #include "llvm/Target/TargetRegistry.h"
using namespace llvm; using namespace llvm;
static cl::opt<bool>
LdStBeforeSched("ldstopti-before-sched2", cl::Hidden,
cl::desc("Move ld / st multiple pass before postalloc scheduling"));
static const MCAsmInfo *createMCAsmInfo(const Target &T, static const MCAsmInfo *createMCAsmInfo(const Target &T,
const StringRef &TT) { const StringRef &TT) {
Triple TheTriple(TT); Triple TheTriple(TT);
@ -109,8 +105,7 @@ bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) { CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1. // FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
if (LdStBeforeSched) PM.add(createARMLoadStoreOptimizationPass());
PM.add(createARMLoadStoreOptimizationPass());
return true; return true;
} }
@ -118,11 +113,8 @@ bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM, bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) { CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1. // FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) { if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
if (!LdStBeforeSched)
PM.add(createARMLoadStoreOptimizationPass());
PM.add(createIfConverterPass()); PM.add(createIfConverterPass());
}
if (Subtarget.isThumb2()) { if (Subtarget.isThumb2()) {
PM.add(createThumb2ITBlockPass()); PM.add(createThumb2ITBlockPass());

2
test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=arm-apple-darwin9 -stats |& grep asm-printer | grep 159 ; RUN: llc < %s -mtriple=arm-apple-darwin9 -stats |& grep asm-printer | grep 154
%"struct.Adv5::Ekin<3>" = type <{ i8 }> %"struct.Adv5::Ekin<3>" = type <{ i8 }>
%"struct.Adv5::X::Energyflux<3>" = type { double } %"struct.Adv5::X::Energyflux<3>" = type { double }

5
test/CodeGen/ARM/2009-09-01-PostRAProlog.ll
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@ -1,8 +1,5 @@
; XFAIL: * ; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s
; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler | FileCheck %s
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
target triple = "thumbv7-apple-darwin9" target triple = "thumbv7-apple-darwin9"

5
test/CodeGen/ARM/ifcvt5.ll
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@ -1,5 +1,4 @@
; RUN: llc < %s -march=arm ; RUN: llc < %s -march=arm | FileCheck %s
; RUN: llc < %s -march=arm | grep blge | count 1
@x = external global i32* ; <i32**> [#uses=1] @x = external global i32* ; <i32**> [#uses=1]
@ -11,6 +10,8 @@ entry:
} }
define void @t1(i32 %a, i32 %b) { define void @t1(i32 %a, i32 %b) {
; CHECK: t1:
; CHECK: ldmltfd sp!, {r7, pc}
entry: entry:
%tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1] %tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1]
br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock