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Add missing const qualifiers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37342 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2007-05-29 18:42:18 +00:00
parent f277ee4be7
commit 62ccdbf0b3
4 changed files with 24 additions and 19 deletions
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20
lib/Target/ARM/ARMInstrInfo.cpp
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@ -431,13 +431,13 @@ ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
return false; return false;
} }
bool ARMInstrInfo::isPredicated(MachineInstr *MI) const { bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
MachineOperand *PMO = MI->findFirstPredOperand(); int PIdx = MI->findFirstPredOperandIdx();
return PMO && PMO->getImmedValue() != ARMCC::AL; return PIdx != -1 && MI->getOperand(PIdx).getImmedValue() != ARMCC::AL;
} }
bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI, bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const { const std::vector<MachineOperand> &Pred) const {
unsigned Opc = MI->getOpcode(); unsigned Opc = MI->getOpcode();
if (Opc == ARM::B || Opc == ARM::tB) { if (Opc == ARM::B || Opc == ARM::tB) {
MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc)); MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
@ -445,16 +445,18 @@ bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
return true; return true;
} }
MachineOperand *PMO = MI->findFirstPredOperand(); int PIdx = MI->findFirstPredOperandIdx();
if (PMO) { if (PIdx != -1) {
PMO->setImm(Pred[0].getImmedValue()); MachineOperand &PMO = MI->getOperand(PIdx);
PMO.setImm(Pred[0].getImmedValue());
return true; return true;
} }
return false; return false;
} }
bool ARMInstrInfo::SubsumesPredicate(std::vector<MachineOperand> &Pred1, bool
std::vector<MachineOperand> &Pred2) const{ ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
const std::vector<MachineOperand> &Pred2) const{
if (Pred1.size() > 1 || Pred2.size() > 1) if (Pred1.size() > 1 || Pred2.size() > 1)
return false; return false;

12
lib/Target/ARM/ARMInstrInfo.h
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@ -104,13 +104,15 @@ public:
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
// Predication support. // Predication support.
virtual bool isPredicated(MachineInstr *MI) const; virtual bool isPredicated(const MachineInstr *MI) const;
virtual bool PredicateInstruction(MachineInstr *MI, virtual
std::vector<MachineOperand> &Pred) const; bool PredicateInstruction(MachineInstr *MI,
const std::vector<MachineOperand> &Pred) const;
virtual bool SubsumesPredicate(std::vector<MachineOperand> &Pred1, virtual
std::vector<MachineOperand> &Pred1) const; bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
const std::vector<MachineOperand> &Pred1) const;
}; };
// Utility routines // Utility routines

5
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -245,8 +245,9 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
/// getInstrPredicate - If instruction is predicated, returns its predicate /// getInstrPredicate - If instruction is predicated, returns its predicate
/// condition, otherwise returns AL. /// condition, otherwise returns AL.
static ARMCC::CondCodes getInstrPredicate(MachineInstr *MI) { static ARMCC::CondCodes getInstrPredicate(MachineInstr *MI) {
MachineOperand *PredMO = MI->findFirstPredOperand(); int PIdx = MI->findFirstPredOperandIdx();
return PredMO ? (ARMCC::CondCodes)PredMO->getImmedValue() : ARMCC::AL; return PIdx == -1 ? ARMCC::AL
: (ARMCC::CondCodes)MI->getOperand(PIdx).getImmedValue();
} }
static inline bool isMatchingDecrement(MachineInstr *MI, unsigned Base, static inline bool isMatchingDecrement(MachineInstr *MI, unsigned Base,

6
lib/Target/ARM/ARMRegisterInfo.cpp
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@ -1009,9 +1009,9 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
if (ScratchReg == 0) if (ScratchReg == 0)
// No register is "free". Scavenge a register. // No register is "free". Scavenge a register.
ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj); ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
MachineOperand *MO = MI.findFirstPredOperand(); int PIdx = MI.findFirstPredOperandIdx();
ARMCC::CondCodes Pred = MO ? ARMCC::CondCodes Pred = (PIdx == -1)
(ARMCC::CondCodes)MO->getImmedValue() : ARMCC::AL; ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImmedValue();
emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, Pred, emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, Pred,
isSub ? -Offset : Offset, TII); isSub ? -Offset : Offset, TII);
MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);