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s tightens up the encoding description for ARM post-indexed ldr instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180778 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mihai Popa
2013-04-30 09:00:12 +00:00
parent defce4cfd6
commit 62d77858be
2 changed files with 1 additions and 1 deletions
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1
lib/Target/ARM/ARMInstrInfo.td
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@@ -2313,6 +2313,7 @@ multiclass AI2_ldridx<bit isByte, string opc,
let Inst{23} = offset{12}; let Inst{23} = offset{12};
let Inst{19-16} = addr; let Inst{19-16} = addr;
let Inst{11-0} = offset{11-0}; let Inst{11-0} = offset{11-0};
let Inst{4} = 0;
let DecoderMethod = "DecodeAddrMode2IdxInstruction"; let DecoderMethod = "DecodeAddrMode2IdxInstruction";
} }

1
test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt
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@@ -1,5 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
# XFAIL: *
# LDR_PRE/POST has encoding Inst{4} = 0. # LDR_PRE/POST has encoding Inst{4} = 0.
0xde 0x69 0x18 0x46 0xde 0x69 0x18 0x46