From 62dd074fe9b4399c3ca18e20eef0f367c0af9348 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Wed, 25 Mar 2015 17:34:11 +0000 Subject: [PATCH] use update_llc_test_checks.py to tighten checking in these tests 1. There were no CHECK-LABELs, so we could match instructions from the wrong function. 2. The use of zero operands meant multiple xor instructions could match some CHECKs. 3. The test was over-specified to need a Sandybridge CPU and Darwin triple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233198 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/avx-logic.ll | 110 ++++++++++++++++++++++++++++------ 1 file changed, 91 insertions(+), 19 deletions(-) diff --git a/test/CodeGen/X86/avx-logic.ll b/test/CodeGen/X86/avx-logic.ll index 062956fbbc6..e71ac473b44 100644 --- a/test/CodeGen/X86/avx-logic.ll +++ b/test/CodeGen/X86/avx-logic.ll @@ -1,7 +1,12 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s -; CHECK: vandpd define <4 x double> @andpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +; CHECK-LABEL: andpd256: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vandpd %ymm0, %ymm1, %ymm0 +; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 +; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 +; CHECK-NEXT: retq entry: %0 = bitcast <4 x double> %x to <4 x i64> %1 = bitcast <4 x double> %y to <4 x i64> @@ -12,8 +17,13 @@ entry: ret <4 x double> %3 } -; CHECK: vandpd LCP{{.*}}(%rip) define <4 x double> @andpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { +; CHECK-LABEL: andpd256fold: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm0 +; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 +; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 +; CHECK-NEXT: retq entry: %0 = bitcast <4 x double> %y to <4 x i64> %and.i = and <4 x i64> %0, @@ -23,8 +33,11 @@ entry: ret <4 x double> %2 } -; CHECK: vandps define <8 x float> @andps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +; CHECK-LABEL: andps256: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vandps %ymm0, %ymm1, %ymm0 +; CHECK-NEXT: retq entry: %0 = bitcast <8 x float> %x to <8 x i32> %1 = bitcast <8 x float> %y to <8 x i32> @@ -33,8 +46,11 @@ entry: ret <8 x float> %2 } -; CHECK: vandps LCP{{.*}}(%rip) define <8 x float> @andps256fold(<8 x float> %y) nounwind uwtable readnone ssp { +; CHECK-LABEL: andps256fold: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 +; CHECK-NEXT: retq entry: %0 = bitcast <8 x float> %y to <8 x i32> %and.i = and <8 x i32> %0, @@ -42,8 +58,13 @@ entry: ret <8 x float> %1 } -; CHECK: vxorpd define <4 x double> @xorpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +; CHECK-LABEL: xorpd256: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vxorpd %ymm0, %ymm1, %ymm0 +; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 +; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 +; CHECK-NEXT: retq entry: %0 = bitcast <4 x double> %x to <4 x i64> %1 = bitcast <4 x double> %y to <4 x i64> @@ -54,8 +75,13 @@ entry: ret <4 x double> %3 } -; CHECK: vxorpd LCP{{.*}}(%rip) define <4 x double> @xorpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { +; CHECK-LABEL: xorpd256fold: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vxorpd {{.*}}(%rip), %ymm0, %ymm0 +; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 +; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 +; CHECK-NEXT: retq entry: %0 = bitcast <4 x double> %y to <4 x i64> %xor.i = xor <4 x i64> %0, @@ -65,8 +91,11 @@ entry: ret <4 x double> %2 } -; CHECK: vxorps define <8 x float> @xorps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +; CHECK-LABEL: xorps256: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vxorps %ymm0, %ymm1, %ymm0 +; CHECK-NEXT: retq entry: %0 = bitcast <8 x float> %x to <8 x i32> %1 = bitcast <8 x float> %y to <8 x i32> @@ -75,8 +104,11 @@ entry: ret <8 x float> %2 } -; CHECK: vxorps LCP{{.*}}(%rip) define <8 x float> @xorps256fold(<8 x float> %y) nounwind uwtable readnone ssp { +; CHECK-LABEL: xorps256fold: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0 +; CHECK-NEXT: retq entry: %0 = bitcast <8 x float> %y to <8 x i32> %xor.i = xor <8 x i32> %0, @@ -84,8 +116,13 @@ entry: ret <8 x float> %1 } -; CHECK: vorpd define <4 x double> @orpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +; CHECK-LABEL: orpd256: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vorpd %ymm0, %ymm1, %ymm0 +; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 +; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 +; CHECK-NEXT: retq entry: %0 = bitcast <4 x double> %x to <4 x i64> %1 = bitcast <4 x double> %y to <4 x i64> @@ -96,8 +133,13 @@ entry: ret <4 x double> %3 } -; CHECK: vorpd LCP{{.*}}(%rip) define <4 x double> @orpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { +; CHECK-LABEL: orpd256fold: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vorpd {{.*}}(%rip), %ymm0, %ymm0 +; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 +; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 +; CHECK-NEXT: retq entry: %0 = bitcast <4 x double> %y to <4 x i64> %or.i = or <4 x i64> %0, @@ -107,8 +149,11 @@ entry: ret <4 x double> %2 } -; CHECK: vorps define <8 x float> @orps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +; CHECK-LABEL: orps256: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vorps %ymm0, %ymm1, %ymm0 +; CHECK-NEXT: retq entry: %0 = bitcast <8 x float> %x to <8 x i32> %1 = bitcast <8 x float> %y to <8 x i32> @@ -117,8 +162,11 @@ entry: ret <8 x float> %2 } -; CHECK: vorps LCP{{.*}}(%rip) define <8 x float> @orps256fold(<8 x float> %y) nounwind uwtable readnone ssp { +; CHECK-LABEL: orps256fold: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vorps {{.*}}(%rip), %ymm0, %ymm0 +; CHECK-NEXT: retq entry: %0 = bitcast <8 x float> %y to <8 x i32> %or.i = or <8 x i32> %0, @@ -126,8 +174,13 @@ entry: ret <8 x float> %1 } -; CHECK: vandnpd define <4 x double> @andnotpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +; CHECK-LABEL: andnotpd256: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vandnpd %ymm0, %ymm1, %ymm0 +; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 +; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 +; CHECK-NEXT: retq entry: %0 = bitcast <4 x double> %x to <4 x i64> %neg.i = xor <4 x i64> %0, @@ -139,8 +192,13 @@ entry: ret <4 x double> %3 } -; CHECK: vandnpd (% define <4 x double> @andnotpd256fold(<4 x double> %y, <4 x double>* nocapture %x) nounwind uwtable readonly ssp { +; CHECK-LABEL: andnotpd256fold: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vandnpd (%rdi), %ymm0, %ymm0 +; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 +; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 +; CHECK-NEXT: retq entry: %tmp2 = load <4 x double>, <4 x double>* %x, align 32 %0 = bitcast <4 x double> %y to <4 x i64> @@ -153,8 +211,11 @@ entry: ret <4 x double> %3 } -; CHECK: vandnps define <8 x float> @andnotps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +; CHECK-LABEL: andnotps256: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vandnps %ymm0, %ymm1, %ymm0 +; CHECK-NEXT: retq entry: %0 = bitcast <8 x float> %x to <8 x i32> %neg.i = xor <8 x i32> %0, @@ -164,8 +225,11 @@ entry: ret <8 x float> %2 } -; CHECK: vandnps (% define <8 x float> @andnotps256fold(<8 x float> %y, <8 x float>* nocapture %x) nounwind uwtable readonly ssp { +; CHECK-LABEL: andnotps256fold: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vandnps (%rdi), %ymm0, %ymm0 +; CHECK-NEXT: retq entry: %tmp2 = load <8 x float>, <8 x float>* %x, align 32 %0 = bitcast <8 x float> %y to <8 x i32> @@ -178,8 +242,12 @@ entry: ;;; Test that basic 2 x i64 logic use the integer version on AVX -; CHECK: vpandn %xmm define <2 x i64> @vpandn(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp { +; CHECK-LABEL: vpandn: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm1 +; CHECK-NEXT: vpandn %xmm0, %xmm1, %xmm0 +; CHECK-NEXT: retq entry: ; Force the execution domain with an add. %a2 = add <2 x i64> %a, @@ -188,8 +256,12 @@ entry: ret <2 x i64> %x } -; CHECK: vpand %xmm define <2 x i64> @vpand(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp { +; CHECK-LABEL: vpand: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0 +; CHECK-NEXT: vpand %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: retq entry: ; Force the execution domain with an add. %a2 = add <2 x i64> %a,