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[AArch64 NEON] Add missing patterns for bitcast from or to v1f64

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199070 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Qin 2014-01-13 01:58:38 +00:00
parent 5c8b8e61df
commit 63735e79ff
2 changed files with 114 additions and 0 deletions
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14
lib/Target/AArch64/AArch64InstrNEON.td
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@ -6222,6 +6222,20 @@ def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
def : Pat<(v1i64 (bitconvert (v1f64 VPR64:$src))), (v1i64 VPR64:$src)>;
def : Pat<(v2f32 (bitconvert (v1f64 VPR64:$src))), (v2f32 VPR64:$src)>;
def : Pat<(v2i32 (bitconvert (v1f64 VPR64:$src))), (v2i32 VPR64:$src)>;
def : Pat<(v4i16 (bitconvert (v1f64 VPR64:$src))), (v4i16 VPR64:$src)>;
def : Pat<(v8i8 (bitconvert (v1f64 VPR64:$src))), (v8i8 VPR64:$src)>;
def : Pat<(f64 (bitconvert (v1f64 VPR64:$src))), (f64 VPR64:$src)>;
def : Pat<(v1f64 (bitconvert (v1i64 VPR64:$src))), (v1f64 VPR64:$src)>;
def : Pat<(v1f64 (bitconvert (v2f32 VPR64:$src))), (v1f64 VPR64:$src)>;
def : Pat<(v1f64 (bitconvert (v2i32 VPR64:$src))), (v1f64 VPR64:$src)>;
def : Pat<(v1f64 (bitconvert (v4i16 VPR64:$src))), (v1f64 VPR64:$src)>;
def : Pat<(v1f64 (bitconvert (v8i8 VPR64:$src))), (v1f64 VPR64:$src)>;
def : Pat<(v1f64 (bitconvert (f64 VPR64:$src))), (v1f64 VPR64:$src)>;
// ..and 128-bit vector bitcasts...
def : Pat<(v2f64 (bitconvert (v16i8 VPR128:$src))), (v2f64 VPR128:$src)>;

100
test/CodeGen/AArch64/neon-copy.ll
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@ -614,6 +614,106 @@ define <1 x double> @test_bitcasti64tov1f64(i64 %in) {
ret <1 x double> %res
}
define <1 x i64> @test_bitcastv8i8tov1f64(<8 x i8> %a) #0 {
; CHECK-LABEL: test_bitcastv8i8tov1f64:
; CHECK: neg {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
; CHECK-NEXT: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}
%sub.i = sub <8 x i8> zeroinitializer, %a
%1 = bitcast <8 x i8> %sub.i to <1 x double>
%vcvt.i = fptosi <1 x double> %1 to <1 x i64>
ret <1 x i64> %vcvt.i
}
define <1 x i64> @test_bitcastv4i16tov1f64(<4 x i16> %a) #0 {
; CHECK-LABEL: test_bitcastv4i16tov1f64:
; CHECK: neg {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
; CHECK-NEXT: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}
%sub.i = sub <4 x i16> zeroinitializer, %a
%1 = bitcast <4 x i16> %sub.i to <1 x double>
%vcvt.i = fptosi <1 x double> %1 to <1 x i64>
ret <1 x i64> %vcvt.i
}
define <1 x i64> @test_bitcastv2i32tov1f64(<2 x i32> %a) #0 {
; CHECK-LABEL: test_bitcastv2i32tov1f64:
; CHECK: neg {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
; CHECK-NEXT: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}
%sub.i = sub <2 x i32> zeroinitializer, %a
%1 = bitcast <2 x i32> %sub.i to <1 x double>
%vcvt.i = fptosi <1 x double> %1 to <1 x i64>
ret <1 x i64> %vcvt.i
}
define <1 x i64> @test_bitcastv1i64tov1f64(<1 x i64> %a) #0 {
; CHECK-LABEL: test_bitcastv1i64tov1f64:
; CHECK: neg {{d[0-9]+}}, {{d[0-9]+}}
; CHECK-NEXT: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}
%sub.i = sub <1 x i64> zeroinitializer, %a
%1 = bitcast <1 x i64> %sub.i to <1 x double>
%vcvt.i = fptosi <1 x double> %1 to <1 x i64>
ret <1 x i64> %vcvt.i
}
define <1 x i64> @test_bitcastv2f32tov1f64(<2 x float> %a) #0 {
; CHECK-LABEL: test_bitcastv2f32tov1f64:
; CHECK: fneg {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
; CHECK-NEXT: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}
%sub.i = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %a
%1 = bitcast <2 x float> %sub.i to <1 x double>
%vcvt.i = fptosi <1 x double> %1 to <1 x i64>
ret <1 x i64> %vcvt.i
}
define <8 x i8> @test_bitcastv1f64tov8i8(<1 x i64> %a) #0 {
; CHECK-LABEL: test_bitcastv1f64tov8i8:
; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
; CHECK-NEXT: neg {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%vcvt.i = sitofp <1 x i64> %a to <1 x double>
%1 = bitcast <1 x double> %vcvt.i to <8 x i8>
%sub.i = sub <8 x i8> zeroinitializer, %1
ret <8 x i8> %sub.i
}
define <4 x i16> @test_bitcastv1f64tov4i16(<1 x i64> %a) #0 {
; CHECK-LABEL: test_bitcastv1f64tov4i16:
; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
; CHECK-NEXT: neg {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
%vcvt.i = sitofp <1 x i64> %a to <1 x double>
%1 = bitcast <1 x double> %vcvt.i to <4 x i16>
%sub.i = sub <4 x i16> zeroinitializer, %1
ret <4 x i16> %sub.i
}
define <2 x i32> @test_bitcastv1f64tov2i32(<1 x i64> %a) #0 {
; CHECK-LABEL: test_bitcastv1f64tov2i32:
; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
; CHECK-NEXT: neg {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%vcvt.i = sitofp <1 x i64> %a to <1 x double>
%1 = bitcast <1 x double> %vcvt.i to <2 x i32>
%sub.i = sub <2 x i32> zeroinitializer, %1
ret <2 x i32> %sub.i
}
define <1 x i64> @test_bitcastv1f64tov1i64(<1 x i64> %a) #0 {
; CHECK-LABEL: test_bitcastv1f64tov1i64:
; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
; CHECK-NEXT: neg {{d[0-9]+}}, {{d[0-9]+}}
%vcvt.i = sitofp <1 x i64> %a to <1 x double>
%1 = bitcast <1 x double> %vcvt.i to <1 x i64>
%sub.i = sub <1 x i64> zeroinitializer, %1
ret <1 x i64> %sub.i
}
define <2 x float> @test_bitcastv1f64tov2f32(<1 x i64> %a) #0 {
; CHECK-LABEL: test_bitcastv1f64tov2f32:
; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
; CHECK-NEXT: fneg {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%vcvt.i = sitofp <1 x i64> %a to <1 x double>
%1 = bitcast <1 x double> %vcvt.i to <2 x float>
%sub.i = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %1
ret <2 x float> %sub.i
}
; Test insert element into an undef vector
define <8 x i8> @scalar_to_vector.v8i8(i8 %a) {
; CHECK-LABEL: scalar_to_vector.v8i8: