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Use the PPC no-r0 class on the TOC LD pseudos

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The register parameter in these instructions becomes the base register in an
r+i ld instruction (and, thus, cannot be r0).

This is not yet testable because we don't yet allocate r0 (and even then any
test would be very fragile).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178121 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2013-03-27 06:36:55 +00:00
parent ab42ec2586
commit 6375e1b87b
1 changed files with 2 additions and 2 deletions
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4
lib/Target/PowerPC/PPCInstr64Bit.td
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@ -680,7 +680,7 @@ def ADDIStocHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, tocentry:$disp),
[(set i64:$rD,
(PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
isPPC64;
def LDtocL: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
def LDtocL: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC_NOX0:$reg),
"#LDtocL",
[(set i64:$rD,
(PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
@ -696,7 +696,7 @@ def ADDISgotTprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$di
(PPCaddisGotTprelHA i64:$reg,
tglobaltlsaddr:$disp))]>,
isPPC64;
def LDgotTprelL: Pseudo<(outs G8RC:$rD), (ins symbolLo64:$disp, G8RC:$reg),
def LDgotTprelL: Pseudo<(outs G8RC:$rD), (ins symbolLo64:$disp, G8RC_NOX0:$reg),
"#LDgotTprelL",
[(set i64:$rD,
(PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,