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R600/SI: Add soffset operand to mubuf addr64 instruction

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We were previously hard-coding soffset to 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228775 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2015-02-11 00:34:32 +00:00
parent a1a22af397
commit 6378a7cb0b
5 changed files with 33 additions and 28 deletions
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5
lib/Target/R600/SIInstrInfo.cpp
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@@ -1729,9 +1729,6 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
assert(SOffset->isImm() && SOffset->getImm() == 0 && "Legalizing MUBUF "
"with non-zero soffset is not implemented");
(void)SOffset;
// Create the new instruction.
unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
@@ -1742,6 +1739,7 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
.addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
// This will be replaced later
// with the new value of vaddr.
.addOperand(*SOffset)
.addOperand(*Offset);
MI->removeFromParent();
@@ -1920,6 +1918,7 @@ void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) con
MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
}
MI->getOperand(1).setReg(SRsrc);
MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0));
MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
const TargetRegisterClass *NewDstRC =