6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-04 05:31:06 +00:00
Code Issues Projects Releases Wiki Activity

Remove simple coalescing.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10695 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alkis Evlogimenos 2004-01-05 08:24:57 +00:00
parent d508776cd5
commit 63caedf046
2 changed files with 0 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -131,21 +131,6 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
assert(r2iit != r2iMap_.end()); assert(r2iit != r2iMap_.end());
intervals_[r2iit->second].weight += pow(10.0F, loopDepth); intervals_[r2iit->second].weight += pow(10.0F, loopDepth);
} }
// add hints for coalescing
unsigned src, dst;
if (tii.isMoveInstr(*instr, src, dst)) {
if (src >= MRegisterInfo::FirstVirtualRegister) {
Reg2IntervalMap::iterator r2iit = r2iMap_.find(src);
assert(r2iit != r2iMap_.end());
intervals_[r2iit->second].hint = dst;
}
if (dst >= MRegisterInfo::FirstVirtualRegister) {
Reg2IntervalMap::iterator r2iit = r2iMap_.find(dst);
assert(r2iit != r2iMap_.end());
intervals_[r2iit->second].hint = src;
}
}
} }
} }

11
lib/CodeGen/RegAllocLinearScan.cpp
View File

@ -617,17 +617,6 @@ unsigned RA::getFreePhysReg(Intervals::const_iterator cur)
DEBUG(std::cerr << "\t\tgetting free physical register: "); DEBUG(std::cerr << "\t\tgetting free physical register: ");
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg); const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg);
if (unsigned reg = cur->hint) {
if (reg >= MRegisterInfo::FirstVirtualRegister &&
v2pMap_.find(reg) != v2pMap_.end())
reg = v2pMap_[reg];
if (reg && reg < MRegisterInfo::FirstVirtualRegister &&
mri_->getRegClass(reg) == rc && !regUse_[reg]) {
DEBUG(std::cerr << mri_->getName(reg) << '\n');
return reg;
}
}
for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_); for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_);
i != rc->allocation_order_end(*mf_); ++i) { i != rc->allocation_order_end(*mf_); ++i) {
unsigned reg = *i; unsigned reg = *i;