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misched: cleanup reaching def computation

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Ignore undef uses completely.
Use a more explicit SlotIndex API.
Add more explicit comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151233 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-02-23 03:16:24 +00:00
parent 5fb468a6b3
commit 63d578b5aa
1 changed files with 5 additions and 3 deletions
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8
lib/CodeGen/ScheduleDAGInstrs.cpp
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@ -408,10 +408,12 @@ void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
// Lookup this operand's reaching definition. // Lookup this operand's reaching definition.
assert(LIS && "vreg dependencies requires LiveIntervals"); assert(LIS && "vreg dependencies requires LiveIntervals");
SlotIndex UseIdx = LIS->getSlotIndexes()->getInstructionIndex(MI); SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot();
LiveInterval *LI = &LIS->getInterval(Reg); LiveInterval *LI = &LIS->getInterval(Reg);
VNInfo *VNI = LI->getVNInfoAt(UseIdx); VNInfo *VNI = LI->getVNInfoBefore(UseIdx);
// VNI will be valid because MachineOperand::readsReg() is checked by caller.
MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def); MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
// Phis and other noninstructions (after coalescing) have a NULL Def.
if (Def) { if (Def) {
SUnit *DefSU = getSUnit(Def); SUnit *DefSU = getSUnit(Def);
if (DefSU) { if (DefSU) {
@ -540,7 +542,7 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
assert(!IsPostRA && "Virtual register encountered!"); assert(!IsPostRA && "Virtual register encountered!");
if (MO.isDef()) if (MO.isDef())
addVRegDefDeps(SU, j); addVRegDefDeps(SU, j);
else else if (MO.readsReg()) // ignore undef operands
addVRegUseDeps(SU, j); addVRegUseDeps(SU, j);
} }
} }