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ARM: force soft-float ABI for tests depending on it.

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This should fix the ARM bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197555 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2013-12-18 09:58:06 +00:00
parent e66345aed4
commit 645efd763d
11 changed files with 14 additions and 14 deletions
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2
test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s ; RUN: llc < %s -march=arm -float-abi=soft -mcpu=cortex-a9 | FileCheck %s
@A = global <4 x float> <float 0., float 1., float 2., float 3.> @A = global <4 x float> <float 0., float 1., float 2., float 3.>

2
test/CodeGen/ARM/fp.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+vfp2 | FileCheck %s
define float @f(i32 %a) { define float @f(i32 %a) {
;CHECK-LABEL: f: ;CHECK-LABEL: f:

2
test/CodeGen/ARM/fpmem.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+vfp2 | FileCheck %s
define float @f1(float %a) { define float @f1(float %a) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:

2
test/CodeGen/ARM/inlineasm3.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm -mattr=+neon,+v6t2 | FileCheck %s ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon,+v6t2 | FileCheck %s
; Radar 7449043 ; Radar 7449043
%struct.int32x4_t = type { <4 x i32> } %struct.int32x4_t = type { <4 x i32> }

2
test/CodeGen/ARM/neon_ld1.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
; CHECK: t1 ; CHECK: t1
; CHECK: vldr d ; CHECK: vldr d

4
test/CodeGen/ARM/neon_ld2.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s --check-prefix=SWIFT ; RUN: llc < %s -march=arm -float-abi=soft -mcpu=swift | FileCheck %s --check-prefix=SWIFT
; CHECK: t1 ; CHECK: t1
; CHECK: vld1.64 ; CHECK: vld1.64

2
test/CodeGen/ARM/vcombine.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK: vcombine8 ; CHECK: vcombine8

2
test/CodeGen/ARM/vdup.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
define <8 x i8> @v_dup8(i8 %A) nounwind { define <8 x i8> @v_dup8(i8 %A) nounwind {
;CHECK-LABEL: v_dup8: ;CHECK-LABEL: v_dup8:

4
test/CodeGen/ARM/vld1.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon -regalloc=basic | FileCheck %s
define <8 x i8> @vld1i8(i8* %A) nounwind { define <8 x i8> @vld1i8(i8* %A) nounwind {
;CHECK-LABEL: vld1i8: ;CHECK-LABEL: vld1i8:

2
test/CodeGen/ARM/vlddup.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
define <8 x i8> @vld1dupi8(i8* %A) nounwind { define <8 x i8> @vld1dupi8(i8* %A) nounwind {
;CHECK-LABEL: vld1dupi8: ;CHECK-LABEL: vld1dupi8:

4
test/CodeGen/ARM/vldlane.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon -regalloc=basic | FileCheck %s
define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind { define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: vld1lanei8: ;CHECK-LABEL: vld1lanei8: