6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-11-04 05:17:07 +00:00
Code Issues Projects Releases Wiki Activity

Some small clean-up: use of pseudo instructions

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110954 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
2010-08-12 20:55:18 +00:00
parent 1adc40cac3
commit 64baddc0f2
1 changed files with 23 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

43
lib/Target/X86/X86InstrSSE.td
View File

@@ -2174,33 +2174,33 @@ def : Pat<(X86SFence), (SFENCE)>;
// Alias instructions that map zero vector to pxor / xorp* for sse. // Alias instructions that map zero vector to pxor / xorp* for sse.
// We set canFoldAsLoad because this can be converted to a constant-pool // We set canFoldAsLoad because this can be converted to a constant-pool
// load of an all-zeros value if folding it would be beneficial. // load of an all-zeros value if folding it would be beneficial.
// FIXME: Change encoding to pseudo!
let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
isCodeGenOnly = 1 in { isCodeGenOnly = 1 in {
def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", let Predicates = [HasSSE1] in
def V_SET0PS : I<0, Pseudo, (outs VR128:$dst), (ins), "",
[(set VR128:$dst, (v4f32 immAllZerosV))]>; [(set VR128:$dst, (v4f32 immAllZerosV))]>;
def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", let Predicates = [HasSSE2] in {
def V_SET0PD : I<0, Pseudo, (outs VR128:$dst), (ins), "",
[(set VR128:$dst, (v2f64 immAllZerosV))]>; [(set VR128:$dst, (v2f64 immAllZerosV))]>;
let ExeDomain = SSEPackedInt in def V_SET0PI : I<0, Pseudo, (outs VR128:$dst), (ins), "",
def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "", [(set VR128:$dst, (v4i32 immAllZerosV))], SSEPackedInt>;
[(set VR128:$dst, (v4i32 immAllZerosV))]>; }
} }
// The same as done above but for AVX. The 128-bit versions are the // The same as done above but for AVX. The 128-bit versions are the
// same, but re-encoded. The 256-bit does not support PI version. // same, but re-encoded. The 256-bit does not support PI version.
let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
isCodeGenOnly = 1, Predicates = [HasAVX] in { isCodeGenOnly = 1, Predicates = [HasAVX] in {
def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", def AVX_SET0PS : I<0, Pseudo, (outs VR128:$dst), (ins), "",
[(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V; [(set VR128:$dst, (v4f32 immAllZerosV))]>;
def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", def AVX_SET0PD : I<0, Pseudo, (outs VR128:$dst), (ins), "",
[(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V; [(set VR128:$dst, (v2f64 immAllZerosV))]>;
def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "", def AVX_SET0PI : I<0, Pseudo, (outs VR128:$dst), (ins), "",
[(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V; [(set VR128:$dst, (v4i32 immAllZerosV))], SSEPackedInt>;
def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "", def AVX_SET0PSY : I<0, Pseudo, (outs VR256:$dst), (ins), "",
[(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V; [(set VR256:$dst, (v8f32 immAllZerosV))]>;
let ExeDomain = SSEPackedInt in def AVX_SET0PDY : I<0, Pseudo, (outs VR256:$dst), (ins), "",
def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "", [(set VR256:$dst, (v4f64 immAllZerosV))]>;
[(set VR128:$dst, (v4i32 immAllZerosV))]>;
} }
def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>; def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
@@ -3249,14 +3249,13 @@ def : Pat<(X86MFence), (MFENCE)>;
// was introduced with SSE2, it's backward compatible. // was introduced with SSE2, it's backward compatible.
def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP; def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
// Alias instructions that map zero vector to pxor / xorp* for sse. // Alias instructions that map one vector to pcmpeqd for sse2 and above.
// We set canFoldAsLoad because this can be converted to a constant-pool // We set canFoldAsLoad because this can be converted to a constant-pool
// load of an all-ones value if folding it would be beneficial. // load of an all-ones value if folding it would be beneficial.
let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
isCodeGenOnly = 1, ExeDomain = SSEPackedInt in isCodeGenOnly = 1, Predicates = [HasSSE2] in
// FIXME: Change encoding to pseudo. def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "", [(set VR128:$dst, (v4i32 immAllOnesV))], SSEPackedInt>;
[(set VR128:$dst, (v4i32 immAllOnesV))]>;
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
// SSE3 - Conversion Instructions // SSE3 - Conversion Instructions