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add patterns for VANDC/VNOR, implementing

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CodeGen/PowerPC/eqv-andc-orc-nor.ll:VNOR/VANDC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27135 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-03-25 23:05:29 +00:00
parent 39e41d6feb
commit 6509ae859a
1 changed files with 8 additions and 3 deletions
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11
lib/Target/PowerPC/PPCInstrAltivec.td
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@ -163,7 +163,7 @@ def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
[(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>; [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
"vandc $vD, $vA, $vB", VecFP, "vandc $vD, $vA, $vB", VecFP,
[]>; [(set VRRC:$vD, (vnot (and (v4i32 VRRC:$vA), VRRC:$vB)))]>;
def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
"vcfsx $vD, $vB, $UIMM", VecFP, "vcfsx $vD, $vB, $UIMM", VecFP,
@ -214,7 +214,7 @@ def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
[(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>; [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
"vnor $vD, $vA, $vB", VecFP, "vnor $vD, $vA, $vB", VecFP,
[]>; [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
"vor $vD, $vA, $vB", VecFP, "vor $vD, $vA, $vB", VecFP,
[(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>; [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
@ -313,7 +313,12 @@ def : Pat<(v16i8 (or VRRC:$A, VRRC:$B)), (v16i8 (VOR VRRC:$A, VRRC:$B))>;
def : Pat<(v8i16 (or VRRC:$A, VRRC:$B)), (v8i16 (VOR VRRC:$A, VRRC:$B))>; def : Pat<(v8i16 (or VRRC:$A, VRRC:$B)), (v8i16 (VOR VRRC:$A, VRRC:$B))>;
def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>; def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>;
def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>; def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>;
def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>;
def : Pat<(v8i16 (vnot (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>;
def : Pat<(v16i8 (vnot (and VRRC:$A, VRRC:$B))),
(v16i8 (VANDC VRRC:$A, VRRC:$B))>;
def : Pat<(v8i16 (vnot (and VRRC:$A, VRRC:$B))),
(v8i16 (VANDC VRRC:$A, VRRC:$B))>;
def : Pat<(fmul VRRC:$vA, VRRC:$vB), def : Pat<(fmul VRRC:$vA, VRRC:$vB),
(VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>; (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>;