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Make insert position available to MergeOpsUpdate.

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Rearrange arguments.
No functional changes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92053 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2009-12-23 21:28:37 +00:00
parent 3063aed8d2
commit 6528966eae
1 changed files with 25 additions and 24 deletions
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49
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@@ -88,7 +88,10 @@ namespace {
ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
DebugLoc dl, SmallVector<std::pair<unsigned, bool>, 8> &Regs); DebugLoc dl, SmallVector<std::pair<unsigned, bool>, 8> &Regs);
void MergeOpsUpdate(MachineBasicBlock &MBB, void MergeOpsUpdate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, MemOpQueue &MemOps,
unsigned memOpsBegin,
unsigned memOpsEnd,
unsigned insertAfter,
int Offset, int Offset,
unsigned Base, unsigned Base,
bool BaseKill, bool BaseKill,
@@ -97,9 +100,6 @@ namespace {
unsigned PredReg, unsigned PredReg,
unsigned Scratch, unsigned Scratch,
DebugLoc dl, DebugLoc dl,
MemOpQueue &MemOps,
unsigned memOpsFrom,
unsigned memOpsTo,
SmallVector<MachineBasicBlock::iterator, 4> &Merges); SmallVector<MachineBasicBlock::iterator, 4> &Merges);
void MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base, void MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base,
int Opcode, unsigned Size, int Opcode, unsigned Size,
@@ -266,7 +266,10 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
// success. // success.
void ARMLoadStoreOpt:: void ARMLoadStoreOpt::
MergeOpsUpdate(MachineBasicBlock &MBB, MergeOpsUpdate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, MemOpQueue &memOps,
unsigned memOpsBegin,
unsigned memOpsEnd,
unsigned insertAfter,
int Offset, int Offset,
unsigned Base, unsigned Base,
bool BaseKill, bool BaseKill,
@@ -275,27 +278,27 @@ MergeOpsUpdate(MachineBasicBlock &MBB,
unsigned PredReg, unsigned PredReg,
unsigned Scratch, unsigned Scratch,
DebugLoc dl, DebugLoc dl,
MemOpQueue &MemOps,
unsigned memOpsFrom,
unsigned memOpsTo,
SmallVector<MachineBasicBlock::iterator, 4> &Merges) { SmallVector<MachineBasicBlock::iterator, 4> &Merges) {
// First calculate which of the registers should be killed by the merged // First calculate which of the registers should be killed by the merged
// instruction. // instruction.
SmallVector<std::pair<unsigned, bool>, 8> Regs; SmallVector<std::pair<unsigned, bool>, 8> Regs;
for (unsigned i = memOpsFrom; i < memOpsTo; ++i) { for (unsigned i = memOpsBegin; i < memOpsEnd; ++i) {
const MachineOperand &MO = MemOps[i].MBBI->getOperand(0); const MachineOperand &MO = memOps[i].MBBI->getOperand(0);
Regs.push_back(std::make_pair(MO.getReg(), MO.isKill())); Regs.push_back(std::make_pair(MO.getReg(), MO.isKill()));
} }
if (!MergeOps(MBB, MBBI, Offset, Base, BaseKill, Opcode, // Try to do the merge.
MachineBasicBlock::iterator Loc = memOps[insertAfter].MBBI;
Loc++;
if (!MergeOps(MBB, Loc, Offset, Base, BaseKill, Opcode,
Pred, PredReg, Scratch, dl, Regs)) Pred, PredReg, Scratch, dl, Regs))
return; return;
// Merge succeeded, update records. // Merge succeeded, update records.
Merges.push_back(prior(MBBI)); Merges.push_back(prior(Loc));
for (unsigned i = memOpsFrom; i < memOpsTo; ++i) { for (unsigned i = memOpsBegin; i < memOpsEnd; ++i) {
MBB.erase(MemOps[i].MBBI); MBB.erase(memOps[i].MBBI);
MemOps[i].Merged = true; memOps[i].Merged = true;
} }
} }
@@ -310,7 +313,7 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
bool isAM4 = isi32Load(Opcode) || isi32Store(Opcode); bool isAM4 = isi32Load(Opcode) || isi32Store(Opcode);
int Offset = MemOps[SIndex].Offset; int Offset = MemOps[SIndex].Offset;
int SOffset = Offset; int SOffset = Offset;
unsigned Pos = MemOps[SIndex].Position; unsigned insertAfter = SIndex;
MachineBasicBlock::iterator Loc = MemOps[SIndex].MBBI; MachineBasicBlock::iterator Loc = MemOps[SIndex].MBBI;
DebugLoc dl = Loc->getDebugLoc(); DebugLoc dl = Loc->getDebugLoc();
unsigned PReg = Loc->getOperand(0).getReg(); unsigned PReg = Loc->getOperand(0).getReg();
@@ -328,22 +331,20 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
PRegNum = RegNum; PRegNum = RegNum;
} else { } else {
// Can't merge this in. Try merge the earlier ones first. // Can't merge this in. Try merge the earlier ones first.
MergeOpsUpdate(MBB, ++Loc, SOffset, Base, false, Opcode, Pred, PredReg, MergeOpsUpdate(MBB, MemOps, SIndex, i, insertAfter, SOffset,
Scratch, dl, MemOps, SIndex, i, Merges); Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges);
MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch, MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,
MemOps, Merges); MemOps, Merges);
return; return;
} }
if (MemOps[i].Position > Pos) { if (MemOps[i].Position > MemOps[insertAfter].Position)
Pos = MemOps[i].Position; insertAfter = i;
Loc = MemOps[i].MBBI;
}
} }
bool BaseKill = Loc->findRegisterUseOperandIdx(Base, true) != -1; bool BaseKill = Loc->findRegisterUseOperandIdx(Base, true) != -1;
MergeOpsUpdate(MBB, ++Loc, SOffset, Base, BaseKill, Opcode, Pred, PredReg, MergeOpsUpdate(MBB, MemOps, SIndex, MemOps.size(), insertAfter, SOffset,
Scratch, dl, MemOps, SIndex, MemOps.size(), Merges); Base, BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges);
return; return;
} }