Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise

cost modeling for if-conversion.  Now if only we had a way to estimate the misprediction probability.

Adjsut CodeGen/ARM/ifcvt10.ll.  The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114995 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMBaseInstrInfo.cpp

@@ -1203,7 +1203,8 @@ bool ARMBaseInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
   
   // Attempt to estimate the relative costs of predication versus branching.
   float UnpredCost = Probability * NumInstrs;
-  UnpredCost += 2.0; // FIXME: Should model a misprediction cost.
+  UnpredCost += 1.0; // The branch itself
+  UnpredCost += 0.1 * Subtarget.getMispredictionPenalty();
   
   float PredCost = NumInstrs;
   
@@ -1220,7 +1221,8 @@ isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
   
   // Attempt to estimate the relative costs of predication versus branching.
   float UnpredCost = Probability * NumT + (1.0 - Probability) * NumF;
-  UnpredCost += 2.0; // FIXME: Should model a misprediction cost.
+  UnpredCost += 1.0; // The branch itself
+  UnpredCost += 0.1 * Subtarget.getMispredictionPenalty();
   
   float PredCost = NumT + NumF;
   

lib/Target/ARM/ARMSubtarget.cpp

@@ -185,6 +185,18 @@ ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
   return false;
 }
 
+unsigned ARMSubtarget::getMispredictionPenalty() const {
+  // If we have a reasonable estimate of the pipeline depth, then we can
+  // estimate the penalty of a misprediction based on that.
+  if (isCortexA8())
+    return 13;
+  else if (isCortexA9())
+    return 8;
+  
+  // Otherwise, just return a sensible default.
+  return 10;
+}
+
 bool ARMSubtarget::enablePostRAScheduler(
            CodeGenOpt::Level OptLevel,
            TargetSubtarget::AntiDepBreakMode& Mode,

lib/Target/ARM/ARMSubtarget.h

@@ -194,6 +194,8 @@ protected:
 
   const std::string & getCPUString() const { return CPUString; }
 
+  unsigned getMispredictionPenalty() const;
+  
   /// enablePostRAScheduler - True at 'More' optimization.
   bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
                              TargetSubtarget::AntiDepBreakMode& Mode,

test/CodeGen/ARM/ifcvt10.ll

@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s
+; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a9 | FileCheck %s
 ; rdar://8402126
 ; Make sure if-converter is not predicating vldmia and ldmia. These are
 ; micro-coded and would have long issue latency even if predicated on