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https://github.com/c64scene-ar/llvm-6502.git
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Use multiclass for the load instructions with 'base + register offset'
addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168976 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jyotsna Verma
parent
63f932ca3c
commit
65502aa5fd
@ -415,15 +415,103 @@ def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst),
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(i32 IntRegs:$src2)))))]>,
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Requires<[HasV4T]>;
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let AddedComplexity = 40, isPredicable = 1 in
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def LDrid_indexed_shl_V4 : LDInst<(outs DoubleRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
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"$dst=memd($src1+$src2<<#$offset)",
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[(set (i64 DoubleRegs:$dst),
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(i64 (load (add (i32 IntRegs:$src1),
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(shl (i32 IntRegs:$src2),
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u2ImmPred:$offset)))))]>,
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Requires<[HasV4T]>;
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// multiclass for load instructions with base + register offset
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// addressing mode
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multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
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bit isPredNew> {
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let PNewValue = #!if(isPredNew, "new", "") in
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def #NAME# : LDInst2<(outs RC:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
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[]>, Requires<[HasV4T]>;
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}
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multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
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let PredSense = #!if(PredNot, "false", "true") in {
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defm _c#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
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// Predicate new
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defm _cdn#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
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}
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}
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let neverHasSideEffects = 1 in
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multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
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let isPredicable = 1 in
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def #NAME#_V4 : LDInst2<(outs RC:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
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"$dst = "#mnemonic#"($src1+$src2<<#$offset)",
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[]>, Requires<[HasV4T]>;
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let isPredicated = 1 in {
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defm Pt_V4 : ld_idxd_shl_pred<mnemonic, RC, 0 >;
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defm NotPt_V4 : ld_idxd_shl_pred<mnemonic, RC, 1>;
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}
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}
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}
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let addrMode = BaseRegOffset in {
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defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, AddrModeRel;
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defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, AddrModeRel;
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defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
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defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, AddrModeRel;
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defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
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defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, AddrModeRel;
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}
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// 'def pats' for load instructions with base + register offset and non-zero
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// immediate value. Immediate value is used to left-shift the second
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// register operand.
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let AddedComplexity = 40 in {
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def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
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(shl IntRegs:$src2, u2ImmPred:$offset)))),
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(LDrib_indexed_shl_V4 IntRegs:$src1,
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IntRegs:$src2, u2ImmPred:$offset)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
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(shl IntRegs:$src2, u2ImmPred:$offset)))),
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(LDriub_indexed_shl_V4 IntRegs:$src1,
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IntRegs:$src2, u2ImmPred:$offset)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
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(shl IntRegs:$src2, u2ImmPred:$offset)))),
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(LDriub_indexed_shl_V4 IntRegs:$src1,
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IntRegs:$src2, u2ImmPred:$offset)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
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(shl IntRegs:$src2, u2ImmPred:$offset)))),
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(LDrih_indexed_shl_V4 IntRegs:$src1,
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IntRegs:$src2, u2ImmPred:$offset)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
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(shl IntRegs:$src2, u2ImmPred:$offset)))),
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(LDriuh_indexed_shl_V4 IntRegs:$src1,
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IntRegs:$src2, u2ImmPred:$offset)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
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(shl IntRegs:$src2, u2ImmPred:$offset)))),
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(LDriuh_indexed_shl_V4 IntRegs:$src1,
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IntRegs:$src2, u2ImmPred:$offset)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (load (add IntRegs:$src1,
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(shl IntRegs:$src2, u2ImmPred:$offset)))),
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(LDriw_indexed_shl_V4 IntRegs:$src1,
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IntRegs:$src2, u2ImmPred:$offset)>,
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Requires<[HasV4T]>;
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def : Pat <(i64 (load (add IntRegs:$src1,
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(shl IntRegs:$src2, u2ImmPred:$offset)))),
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(LDrid_indexed_shl_V4 IntRegs:$src1,
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IntRegs:$src2, u2ImmPred:$offset)>,
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Requires<[HasV4T]>;
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}
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//// Load doubleword conditionally.
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// if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2)
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@ -459,42 +547,6 @@ def LDrid_indexed_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
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[]>,
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Requires<[HasV4T]>;
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// if (Pv) Rd=memd(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDrid_indexed_shl_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
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u2Imm:$offset),
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"if ($src1) $dst=memd($src2+$src3<<#$offset)",
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[]>,
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Requires<[HasV4T]>;
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// if (Pv.new) Rd=memd(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDrid_indexed_shl_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
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u2Imm:$offset),
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"if ($src1.new) $dst=memd($src2+$src3<<#$offset)",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv) Rd=memd(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDrid_indexed_shl_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
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u2Imm:$offset),
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"if (!$src1) $dst=memd($src2+$src3<<#$offset)",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDrid_indexed_shl_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
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u2Imm:$offset),
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"if (!$src1.new) $dst=memd($src2+$src3<<#$offset)",
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[]>,
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Requires<[HasV4T]>;
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// Rdd=memd(Rt<<#u2+#U6)
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//// Load byte.
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@ -526,26 +578,6 @@ def LDriub_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
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(i32 IntRegs:$src2)))))]>,
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Requires<[HasV4T]>;
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let AddedComplexity = 40, isPredicable = 1 in
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def LDrib_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
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"$dst=memb($src1+$src2<<#$offset)",
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[(set (i32 IntRegs:$dst),
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(i32 (sextloadi8 (add (i32 IntRegs:$src1),
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(shl (i32 IntRegs:$src2),
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u2ImmPred:$offset)))))]>,
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Requires<[HasV4T]>;
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let AddedComplexity = 40, isPredicable = 1 in
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def LDriub_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
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"$dst=memub($src1+$src2<<#$offset)",
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[(set (i32 IntRegs:$dst),
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(i32 (zextloadi8 (add (i32 IntRegs:$src1),
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(shl (i32 IntRegs:$src2),
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u2ImmPred:$offset)))))]>,
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Requires<[HasV4T]>;
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let AddedComplexity = 40, isPredicable = 1 in
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def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
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@ -590,42 +622,6 @@ def LDrib_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
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[]>,
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Requires<[HasV4T]>;
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// if (Pv) Rd=memb(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDrib_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
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u2Imm:$offset),
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"if ($src1) $dst=memb($src2+$src3<<#$offset)",
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[]>,
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Requires<[HasV4T]>;
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// if (Pv.new) Rd=memb(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDrib_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
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u2Imm:$offset),
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"if ($src1.new) $dst=memb($src2+$src3<<#$offset)",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv) Rd=memb(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDrib_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
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u2Imm:$offset),
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"if (!$src1) $dst=memb($src2+$src3<<#$offset)",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDrib_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
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u2Imm:$offset),
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"if (!$src1.new) $dst=memb($src2+$src3<<#$offset)",
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[]>,
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Requires<[HasV4T]>;
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//// Load unsigned byte conditionally.
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// if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2)
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// if (Pv) Rd=memub(Rs+Rt<<#u2)
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@ -660,42 +656,6 @@ def LDriub_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
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[]>,
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Requires<[HasV4T]>;
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// if (Pv) Rd=memub(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDriub_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
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u2Imm:$offset),
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"if ($src1) $dst=memub($src2+$src3<<#$offset)",
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[]>,
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Requires<[HasV4T]>;
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// if (Pv.new) Rd=memub(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDriub_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
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u2Imm:$offset),
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"if ($src1.new) $dst=memub($src2+$src3<<#$offset)",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv) Rd=memub(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDriub_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
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u2Imm:$offset),
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"if (!$src1) $dst=memub($src2+$src3<<#$offset)",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDriub_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
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u2Imm:$offset),
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"if (!$src1.new) $dst=memub($src2+$src3<<#$offset)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memb(Rt<<#u2+#U6)
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//// Load halfword
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@ -727,27 +687,6 @@ def LDriuh_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
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(i32 IntRegs:$src2)))))]>,
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Requires<[HasV4T]>;
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// Rd=memh(Rs+Rt<<#u2)
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let AddedComplexity = 40, isPredicable = 1 in
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def LDrih_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
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"$dst=memh($src1+$src2<<#$offset)",
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[(set (i32 IntRegs:$dst),
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(i32 (sextloadi16 (add (i32 IntRegs:$src1),
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(shl (i32 IntRegs:$src2),
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u2ImmPred:$offset)))))]>,
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Requires<[HasV4T]>;
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let AddedComplexity = 40, isPredicable = 1 in
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def LDriuh_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
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"$dst=memuh($src1+$src2<<#$offset)",
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[(set (i32 IntRegs:$dst),
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(i32 (zextloadi16 (add (i32 IntRegs:$src1),
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(shl (i32 IntRegs:$src2),
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u2ImmPred:$offset)))))]>,
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Requires<[HasV4T]>;
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let AddedComplexity = 40, isPredicable = 1 in
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def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
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@ -792,42 +731,6 @@ def LDrih_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
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[]>,
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Requires<[HasV4T]>;
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// if (Pv) Rd=memh(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDrih_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
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u2Imm:$offset),
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"if ($src1) $dst=memh($src2+$src3<<#$offset)",
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[]>,
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Requires<[HasV4T]>;
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// if (Pv.new) Rd=memh(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDrih_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
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u2Imm:$offset),
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"if ($src1.new) $dst=memh($src2+$src3<<#$offset)",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv) Rd=memh(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDrih_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
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u2Imm:$offset),
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"if (!$src1) $dst=memh($src2+$src3<<#$offset)",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDrih_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
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u2Imm:$offset),
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"if (!$src1.new) $dst=memh($src2+$src3<<#$offset)",
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[]>,
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Requires<[HasV4T]>;
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//// Load unsigned halfword conditionally.
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// if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2)
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// if (Pv) Rd=memuh(Rs+Rt<<#u2)
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@ -862,42 +765,6 @@ def LDriuh_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
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[]>,
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Requires<[HasV4T]>;
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// if (Pv) Rd=memuh(Rs+Rt<<#u2)
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let AddedComplexity = 45, isPredicated = 1 in
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def LDriuh_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst),
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||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
"if ($src1) $dst=memuh($src2+$src3<<#$offset)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriuh_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
"if ($src1.new) $dst=memuh($src2+$src3<<#$offset)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memuh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriuh_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
"if (!$src1) $dst=memuh($src2+$src3<<#$offset)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriuh_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
"if (!$src1.new) $dst=memuh($src2+$src3<<#$offset)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// Rd=memh(Rt<<#u2+#U6)
|
||||
|
||||
//// Load word.
|
||||
@ -921,17 +788,6 @@ def LDriw_indexed_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(i32 IntRegs:$src2)))))]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// Rd=memw(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 40, isPredicable = 1 in
|
||||
def LDriw_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
|
||||
"$dst=memw($src1+$src2<<#$offset)",
|
||||
[(set (i32 IntRegs:$dst),
|
||||
(i32 (load (add (i32 IntRegs:$src1),
|
||||
(shl (i32 IntRegs:$src2),
|
||||
u2ImmPred:$offset)))))]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
//// Load word conditionally.
|
||||
// if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2)
|
||||
// if (Pv) Rd=memw(Rs+Rt<<#u2)
|
||||
@ -966,42 +822,6 @@ def LDriw_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv) Rd=memh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriw_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
"if ($src1) $dst=memw($src2+$src3<<#$offset)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriw_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
"if ($src1.new) $dst=memw($src2+$src3<<#$offset)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriw_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
"if (!$src1) $dst=memw($src2+$src3<<#$offset)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriw_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
"if (!$src1.new) $dst=memw($src2+$src3<<#$offset)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
/// Load from global offset
|
||||
|
||||
let isPredicable = 1, neverHasSideEffects = 1 in
|
||||
|
||||
Loading…
Reference in New Issue
Block a user