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Expand pseudos/macros:

Browse Source 
SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16
$T8 shows up as register $24 when emitted from C++ code so we had
to change some tests that were already there for this functionality.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175593 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler 2013-02-20 05:45:15 +00:00
parent d326d05fb9
commit 65692c809e
16 changed files with 125 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
lib/Target/Mips/Mips16InstrInfo.cpp
View File

@ -184,6 +184,18 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
case Mips::RetRA16:
ExpandRetRA16(MBB, MI, Mips::JrcRa16);
break;
case Mips::SltCCRxRy16:
ExpandFEXT_CCRX16_ins(MBB, MI, Mips::SltRxRy16);
break;
case Mips::SltiCCRxImmX16:
ExpandFEXT_CCRXI16_ins(MBB, MI, Mips::SltiRxImm16, Mips::SltiRxImmX16);
break;
case Mips::SltiuCCRxImmX16:
ExpandFEXT_CCRXI16_ins(MBB, MI, Mips::SltiuRxImm16, Mips::SltiuRxImmX16);
break;
case Mips::SltuCCRxRy16:
ExpandFEXT_CCRX16_ins(MBB, MI, Mips::SltuRxRy16);
break;
}
MBB.erase(MI);
@ -474,6 +486,30 @@ void Mips16InstrInfo::ExpandFEXT_T8I8I16_ins(
BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
}
void Mips16InstrInfo::ExpandFEXT_CCRX16_ins(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SltOpc) const {
unsigned CC = I->getOperand(0).getReg();
unsigned regX = I->getOperand(1).getReg();
unsigned regY = I->getOperand(2).getReg();
BuildMI(MBB, I, I->getDebugLoc(), get(SltOpc)).addReg(regX).addReg(regY);
BuildMI(MBB, I, I->getDebugLoc(),
get(Mips::MoveR3216), CC).addReg(Mips::T8);
}
void Mips16InstrInfo::ExpandFEXT_CCRXI16_ins(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SltiOpc, unsigned SltiXOpc) const {
unsigned CC = I->getOperand(0).getReg();
unsigned regX = I->getOperand(1).getReg();
int64_t Imm = I->getOperand(2).getImm();
unsigned SltOpc = whichOp8u_or_16simm(SltiOpc, SltiXOpc, Imm);
BuildMI(MBB, I, I->getDebugLoc(), get(SltOpc)).addReg(regX).addImm(Imm);
BuildMI(MBB, I, I->getDebugLoc(),
get(Mips::MoveR3216), CC).addReg(Mips::T8);
}
const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
if (validSpImm8(Imm))
return get(Mips::AddiuSpImm16);
@ -487,6 +523,26 @@ void Mips16InstrInfo::BuildAddiuSpImm
BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
}
unsigned Mips16InstrInfo::whichOp8_or_16uimm
(unsigned shortOp, unsigned longOp, int64_t Imm) {
if (isUInt<8>(Imm))
return shortOp;
else if (isUInt<16>(Imm))
return longOp;
else
llvm_unreachable("immediate field not usable");
}
unsigned Mips16InstrInfo::whichOp8u_or_16simm
(unsigned shortOp, unsigned longOp, int64_t Imm) {
if (isUInt<8>(Imm))
return shortOp;
else if (isInt<16>(Imm))
return longOp;
else
llvm_unreachable("immediate field not usable");
}
const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
return new Mips16InstrInfo(TM);
}

14
lib/Target/Mips/Mips16InstrInfo.h
View File

@ -123,6 +123,20 @@ private:
MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc) const;
void ExpandFEXT_CCRX16_ins(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SltOpc) const;
void ExpandFEXT_CCRXI16_ins(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SltiOpc, unsigned SltiXOpc) const;
static unsigned
whichOp8_or_16uimm (unsigned shortOp, unsigned longOp, int64_t Imm);
static unsigned
whichOp8u_or_16simm (unsigned shortOp, unsigned longOp, int64_t Imm);
};
}

50
lib/Target/Mips/Mips16InstrInfo.td
View File

@ -59,7 +59,16 @@ class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
class FRI16_ins<bits<5> op, string asmstr,
InstrItinClass itin>:
FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
InstrItinClass itin>:
FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
!strconcat(asmstr, asmstr2), [], itin>;
class FRI16R_ins<bits<5> op, string asmstr,
InstrItinClass itin>:
FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
class F2RI16_ins<bits<5> _op, string asmstr,
InstrItinClass itin>:
FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
@ -140,6 +149,15 @@ class FEXT_RI16_ins<bits<5> _op, string asmstr,
InstrItinClass itin>:
FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2,
InstrItinClass itin>:
FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm),
!strconcat(asmstr, asmstr2), [], itin>;
class FEXT_RI16R_ins<bits<5> _op, string asmstr,
InstrItinClass itin>:
FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
@ -384,7 +402,7 @@ class SeliT<string op1, string op2>:
//
//
class SelT<string op1, string op2>:
MipsPseudo16<(outs CPU16Regs:$rd_),
MipsPseudo16<(outs CPU16Regs:$rd_),
(ins CPU16Regs:$rd, CPU16Regs:$rs,
CPU16Regs:$rl, CPU16Regs:$rr),
!strconcat(op2,
@ -690,6 +708,13 @@ def LhuRxRyOffMemX16:
let isCodeGenOnly = 1;
}
//
// Format: LI rx, immediate MIPS16e
// Purpose: Load Immediate
// To load a constant into a GPR.
//
def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>;
//
// Format: LI rx, immediate MIPS16e
// Purpose: Load Immediate (Extended)
@ -1017,7 +1042,7 @@ def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
// To record the result of a less-than comparison with a constant.
//
//
def SltiRxImm16: FRI16_ins<0b01010, "slti", IIAlu> {
def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> {
let Defs = [T8];
}
@ -1027,7 +1052,7 @@ def SltiRxImm16: FRI16_ins<0b01010, "slti", IIAlu> {
// To record the result of a less-than comparison with a constant.
//
//
def SltiRxImmX16: FEXT_RI16_ins<0b01010, "slti", IIAlu> {
def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> {
let Defs = [T8];
}
@ -1038,7 +1063,7 @@ def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
// To record the result of a less-than comparison with a constant.
//
//
def SltiuRxImm16: FRI16_ins<0b01011, "sltiu", IIAlu> {
def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> {
let Defs = [T8];
}
@ -1048,7 +1073,7 @@ def SltiuRxImm16: FRI16_ins<0b01011, "sltiu", IIAlu> {
// To record the result of a less-than comparison with a constant.
//
//
def SltiuRxImmX16: FEXT_RI16_ins<0b01011, "sltiu", IIAlu> {
def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> {
let Defs = [T8];
}
//
@ -1063,7 +1088,9 @@ def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
// Purpose: Set on Less Than
// To record the result of a less-than comparison.
//
def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>;
def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>{
let Defs = [T8];
}
def SltCCRxRy16: FCCRR16_ins<"slt">;
@ -1071,10 +1098,13 @@ def SltCCRxRy16: FCCRR16_ins<"slt">;
// Purpose: Set on Less Than Unsigned
// To record the result of an unsigned less-than comparison.
//
def SltuRxRy16: FRR16_ins<0b00011, "sltu", IIAlu>;
def SltuRxRy16: FRR16_ins<0b00011, "sltu", IIAlu>{
let Defs = [T8];
}
def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
let isCodeGenOnly=1;
let Defs = [T8];
}
@ -1648,7 +1678,7 @@ def: Mips16Pat
//
def: Mips16Pat
<(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
(XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
(XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>;
//
// setlt
@ -1708,7 +1738,7 @@ def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
// hi/lo relocs
def : Mips16Pat<(MipsHi tglobaladdr:$in),
def : Mips16Pat<(MipsHi tglobaladdr:$in),
(SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>;
def : Mips16Pat<(MipsHi tjumptable:$in),
(SllX16 (LiRxImmX16 tjumptable:$in), 16)>;

2
test/CodeGen/Mips/seteq.ll
View File

@ -15,7 +15,7 @@ entry:
store i32 %conv, i32* @r1, align 4
; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
; 16: move ${{[0-9]+}}, $t8
; 16: move ${{[0-9]+}}, $24
ret void
}

4
test/CodeGen/Mips/seteqz.ll
View File

@ -12,13 +12,13 @@ entry:
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
; 16: sltiu ${{[0-9]+}}, 1
; 16: move ${{[0-9]+}}, $t8
; 16: move ${{[0-9]+}}, $24
%1 = load i32* @j, align 4
%cmp1 = icmp eq i32 %1, 99
%conv2 = zext i1 %cmp1 to i32
store i32 %conv2, i32* @r2, align 4
; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
; 16: move ${{[0-9]+}}, $t8
; 16: move ${{[0-9]+}}, $24
ret void
}

2
test/CodeGen/Mips/setge.ll
View File

@ -17,7 +17,7 @@ entry:
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
; 16: move $[[REGISTER:[0-9]+]], $t8
; 16: move $[[REGISTER:[0-9]+]], $24
; 16: xor $[[REGISTER]], ${{[0-9]+}}
%2 = load i32* @m, align 4
%cmp1 = icmp sge i32 %0, %2

2
test/CodeGen/Mips/setgek.ll
View File

@ -12,7 +12,7 @@ entry:
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
; 16: slti ${{[0-9]+}}, -32768
; 16: move ${{[0-9]+}}, $t8
; 16: move ${{[0-9]+}}, $24
; 16: xor ${{[0-9]+}}, ${{[0-9]+}}
ret void
}

2
test/CodeGen/Mips/setle.ll
View File

@ -16,7 +16,7 @@ entry:
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
; 16: move $[[REGISTER:[0-9]+]], $t8
; 16: move $[[REGISTER:[0-9]+]], $24
; 16: xor $[[REGISTER]], ${{[0-9]+}}
%2 = load i32* @m, align 4
%cmp1 = icmp sle i32 %2, %1

2
test/CodeGen/Mips/setlt.ll
View File

@ -16,6 +16,6 @@ entry:
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
; 16: move ${{[0-9]+}}, $t8
; 16: move ${{[0-9]+}}, $24
ret void
}

2
test/CodeGen/Mips/setltk.ll
View File

@ -15,6 +15,6 @@ entry:
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
; 16: slti $[[REGISTER:[0-9]+]], 10
; 16: move $[[REGISTER]], $t8
; 16: move $[[REGISTER]], $24
ret void
}

2
test/CodeGen/Mips/setne.ll
View File

@ -15,6 +15,6 @@ entry:
store i32 %conv, i32* @r1, align 4
; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}}
; 16: sltu ${{[0-9]+}}, $[[REGISTER]]
; 16: move ${{[0-9]+}}, $t8
; 16: move ${{[0-9]+}}, $24
ret void
}

2
test/CodeGen/Mips/setuge.ll
View File

@ -16,7 +16,7 @@ entry:
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
; 16: move $[[REGISTER:[0-9]+]], $t8
; 16: move $[[REGISTER:[0-9]+]], $24
; 16: xor $[[REGISTER]], ${{[0-9]+}}
%2 = load i32* @m, align 4
%cmp1 = icmp uge i32 %0, %2

2
test/CodeGen/Mips/setugt.ll
View File

@ -16,6 +16,6 @@ entry:
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
; 16: move ${{[0-9]+}}, $t8
; 16: move ${{[0-9]+}}, $24
ret void
}

2
test/CodeGen/Mips/setule.ll
View File

@ -16,7 +16,7 @@ entry:
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
; 16: move $[[REGISTER:[0-9]+]], $t8
; 16: move $[[REGISTER:[0-9]+]], $24
; 16: xor $[[REGISTER]], ${{[0-9]+}}
%2 = load i32* @m, align 4
%cmp1 = icmp ule i32 %2, %1

2
test/CodeGen/Mips/setult.ll
View File

@ -16,6 +16,6 @@ entry:
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
; 16: move ${{[0-9]+}}, $t8
; 16: move ${{[0-9]+}}, $24
ret void
}

4
test/CodeGen/Mips/setultk.ll
View File

@ -14,7 +14,7 @@ entry:
%cmp = icmp ult i32 %0, 10
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
; 16: sltiu $[[REGISTER:[0-9]+]], 10
; 16: move $[[REGISTER]], $t8
; 16: sltiu ${{[0-9]+}}, 10 # 16 bit inst
; 16: move ${{[0-9]+}}, $24
ret void
}