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misched: Fix RegisterPressureTracker handling of DebugVals.

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Assertion failed: (TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker").
rdar://12790302.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169072 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
2012-12-01 01:22:49 +00:00
parent 177d87ac8d
commit 657b75b994
5 changed files with 74 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
lib/CodeGen/MachineScheduler.cpp
View File

@@ -603,7 +603,11 @@ void ScheduleDAGMI::initQueues() {
SchedImpl->registerRoots();
// Advance past initial DebugValues.
assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker");
CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
TopRPTracker.setPos(CurrentTop);
CurrentBottom = RegionEnd;
}

26
lib/CodeGen/RegisterPressure.cpp
View File

@@ -181,9 +181,6 @@ void RegPressureTracker::init(const MachineFunction *mf,
}
CurrPos = pos;
while (CurrPos != MBB->end() && CurrPos->isDebugValue())
++CurrPos;
CurrSetPressure.assign(TRI->getNumRegPressureSets(), 0);
if (RequireIntervals)
@@ -214,11 +211,20 @@ bool RegPressureTracker::isBottomClosed() const {
MachineBasicBlock::const_iterator());
}
SlotIndex RegPressureTracker::getCurrSlot() const {
MachineBasicBlock::const_iterator IdxPos = CurrPos;
while (IdxPos != MBB->end() && IdxPos->isDebugValue())
++IdxPos;
if (IdxPos == MBB->end())
return LIS->getMBBEndIdx(MBB);
return LIS->getInstructionIndex(IdxPos).getRegSlot();
}
/// Set the boundary for the top of the region and summarize live ins.
void RegPressureTracker::closeTop() {
if (RequireIntervals)
static_cast<IntervalPressure&>(P).TopIdx =
LIS->getInstructionIndex(CurrPos).getRegSlot();
static_cast<IntervalPressure&>(P).TopIdx = getCurrSlot();
else
static_cast<RegionPressure&>(P).TopPos = CurrPos;
@@ -236,11 +242,7 @@ void RegPressureTracker::closeTop() {
/// Set the boundary for the bottom of the region and summarize live outs.
void RegPressureTracker::closeBottom() {
if (RequireIntervals)
if (CurrPos == MBB->end())
static_cast<IntervalPressure&>(P).BottomIdx = LIS->getMBBEndIdx(MBB);
else
static_cast<IntervalPressure&>(P).BottomIdx =
LIS->getInstructionIndex(CurrPos).getRegSlot();
static_cast<IntervalPressure&>(P).BottomIdx = getCurrSlot();
else
static_cast<RegionPressure&>(P).BottomPos = CurrPos;
@@ -510,7 +512,7 @@ bool RegPressureTracker::advance() {
SlotIndex SlotIdx;
if (RequireIntervals)
SlotIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
SlotIdx = getCurrSlot();
// Open the bottom of the region using slot indexes.
if (isBottomClosed()) {
@@ -769,7 +771,7 @@ void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) {
const LiveInterval *LI = &LIS->getInterval(Reg);
// FIXME: allow the caller to pass in the list of vreg uses that remain to
// be bottom-scheduled to avoid searching uses at each query.
SlotIndex CurrIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
SlotIndex CurrIdx = getCurrSlot();
if (LI->killedAt(SlotIdx)
&& !findUseBetween(Reg, CurrIdx, SlotIdx, MRI, LIS)) {
decreaseVirtRegPressure(Reg);

14
lib/CodeGen/ScheduleDAGInstrs.cpp
View File

@@ -713,17 +713,17 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
addSchedBarrierDeps();
// Walk the list of instructions, from bottom moving up.
MachineInstr *PrevMI = NULL;
MachineInstr *DbgMI = NULL;
for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
MII != MIE; --MII) {
MachineInstr *MI = prior(MII);
if (MI && PrevMI) {
DbgValues.push_back(std::make_pair(PrevMI, MI));
PrevMI = NULL;
if (MI && DbgMI) {
DbgValues.push_back(std::make_pair(DbgMI, MI));
DbgMI = NULL;
}
if (MI->isDebugValue()) {
PrevMI = MI;
DbgMI = MI;
continue;
}
if (RPTracker) {
@@ -917,8 +917,8 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
}
}
}
if (PrevMI)
FirstDbgValue = PrevMI;
if (DbgMI)
FirstDbgValue = DbgMI;
Defs.clear();
Uses.clear();