mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-11-01 15:17:25 +00:00
fix oopso
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20056 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -301,6 +301,27 @@ namespace {
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};
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};
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}
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}
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static unsigned GetSymVersion(unsigned opcode)
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{
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switch (opcode) {
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default: assert(0 && "unknown load or store"); return 0;
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case Alpha::LDQ: return Alpha::LDQ_SYM;
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case Alpha::LDS: return Alpha::LDS_SYM;
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case Alpha::LDT: return Alpha::LDT_SYM;
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case Alpha::LDL: return Alpha::LDL_SYM;
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case Alpha::LDBU: return Alpha::LDBU_SYM;
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case Alpha::LDWU: return Alpha::LDWU_SYM;
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case Alpha::LDW: return Alpha::LDW_SYM;
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case Alpha::LDB: return Alpha::LDB_SYM;
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case Alpha::STQ: return Alpha::STQ_SYM;
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case Alpha::STS: return Alpha::STS_SYM;
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case Alpha::STT: return Alpha::STT_SYM;
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case Alpha::STL: return Alpha::STL_SYM;
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case Alpha::STW: return Alpha::STW_SYM;
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case Alpha::STB: return Alpha::STB_SYM;
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}
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}
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//Check to see if the load is a constant offset from a base register
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//Check to see if the load is a constant offset from a base register
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void ISel::SelectAddr(SDOperand N, unsigned& Reg, long& offset)
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void ISel::SelectAddr(SDOperand N, unsigned& Reg, long& offset)
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{
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{
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@@ -399,23 +420,23 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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SDOperand Chain = N.getOperand(0);
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SDOperand Chain = N.getOperand(0);
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SDOperand Address = N.getOperand(1);
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SDOperand Address = N.getOperand(1);
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Select(Chain);
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Select(Chain);
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Opc = DestType == MVT::f64 ? Alpha::LDT : Alpha::LDS;
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if (Address.getOpcode() == ISD::GlobalAddress)
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if (Address.getOpcode() == ISD::GlobalAddress)
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{
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{
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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Opc = DestType == MVT::f64 ? Alpha::LDT_SYM : Alpha::LDS_SYM;
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Opc = GetSymVersion(Opc);
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BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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}
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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Opc = DestType == MVT::f64 ? Alpha::LDT_SYM : Alpha::LDS_SYM;
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Opc = GetSymVersion(Opc);
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BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
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BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
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}
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}
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else
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else
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{
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{
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long offset;
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long offset;
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SelectAddr(Address, Tmp1, offset);
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SelectAddr(Address, Tmp1, offset);
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Opc = DestType == MVT::f64 ? Alpha::LDT : Alpha::LDS;
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BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
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BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
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}
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}
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return Result;
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return Result;
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@@ -597,11 +618,13 @@ unsigned ISel::SelectExpr(SDOperand N) {
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if (Address.getOpcode() == ISD::GlobalAddress)
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if (Address.getOpcode() == ISD::GlobalAddress)
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{
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{
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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Opc = GetSymVersion(Opc);
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BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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}
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address))
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address))
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{
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{
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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Opc = GetSymVersion(Opc);
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BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
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BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
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}
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}
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else
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else
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@@ -637,11 +660,13 @@ unsigned ISel::SelectExpr(SDOperand N) {
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if (Address.getOpcode() == ISD::GlobalAddress)
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if (Address.getOpcode() == ISD::GlobalAddress)
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{
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{
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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Opc = GetSymVersion(Opc);
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BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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}
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
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Opc = GetSymVersion(Opc);
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BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
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}
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}
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else
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else
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{
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{
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@@ -677,10 +702,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
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if (Address.getOpcode() == ISD::GlobalAddress)
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if (Address.getOpcode() == ISD::GlobalAddress)
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{
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{
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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Opc = GetSymVersion(Opc);
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BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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}
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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Opc = GetSymVersion(Opc);
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BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
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BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
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}
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}
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else
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else
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@@ -1326,26 +1353,20 @@ void ISel::Select(SDOperand N) {
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Tmp1 = SelectExpr(Value); //value
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Tmp1 = SelectExpr(Value); //value
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MVT::ValueType DestType = Value.getValueType();
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MVT::ValueType DestType = Value.getValueType();
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switch(DestType) {
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default: assert(0 && "unknown Type in store");
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case MVT::i64: Opc = Alpha::STQ; break;
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case MVT::f64: Opc = Alpha::STT; break;
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case MVT::f32: Opc = Alpha::STS; break;
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}
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if (Address.getOpcode() == ISD::GlobalAddress)
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if (Address.getOpcode() == ISD::GlobalAddress)
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{
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{
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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switch(DestType) {
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Opc = GetSymVersion(Opc);
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default: assert(0 && "unknown Type in store");
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case MVT::i64: Opc = Alpha::STQ_SYM; break;
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case MVT::f64: Opc = Alpha::STT_SYM; break;
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case MVT::f32: Opc = Alpha::STS_SYM; break;
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}
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BuildMI(BB, Opc, 2).addReg(Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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BuildMI(BB, Opc, 2).addReg(Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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}
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else
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else
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{
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{
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switch(DestType) {
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default: assert(0 && "unknown Type in store");
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case MVT::i64: Opc = Alpha::STQ; break;
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case MVT::f64: Opc = Alpha::STT; break;
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case MVT::f32: Opc = Alpha::STS; break;
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}
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long offset;
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long offset;
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SelectAddr(Address, Tmp2, offset);
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SelectAddr(Address, Tmp2, offset);
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BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
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BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
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@@ -1373,30 +1394,24 @@ void ISel::Select(SDOperand N) {
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Select(Chain);
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Select(Chain);
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MVT::ValueType DestType = cast<MVTSDNode>(Node)->getExtraValueType();
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MVT::ValueType DestType = cast<MVTSDNode>(Node)->getExtraValueType();
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switch(DestType) {
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default: assert(0 && "unknown Type in store");
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case MVT::i1: //FIXME: DAG does not promote this load
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case MVT::i8: Opc = Alpha::STB; break;
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case MVT::i16: Opc = Alpha::STW; break;
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case MVT::i32: Opc = Alpha::STL; break;
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}
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Tmp1 = SelectExpr(Value); //value
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Tmp1 = SelectExpr(Value); //value
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if (Address.getOpcode() == ISD::GlobalAddress)
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if (Address.getOpcode() == ISD::GlobalAddress)
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{
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{
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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switch(DestType) {
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Opc = GetSymVersion(Opc);
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default: assert(0 && "unknown Type in store");
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case MVT::i1: //FIXME: DAG does not promote this load
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case MVT::i8: Opc = Alpha::STB; break;
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case MVT::i16: Opc = Alpha::STW; break;
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case MVT::i32: Opc = Alpha::STL; break;
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}
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BuildMI(BB, Opc, 2).addReg(Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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BuildMI(BB, Opc, 2).addReg(Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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}
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else
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else
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{
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{
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switch(DestType) {
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default: assert(0 && "unknown Type in store");
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case MVT::i1: //FIXME: DAG does not promote this load
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case MVT::i8: Opc = Alpha::STB; break;
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case MVT::i16: Opc = Alpha::STW; break;
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case MVT::i32: Opc = Alpha::STL; break;
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}
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long offset;
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long offset;
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SelectAddr(Address, Tmp2, offset);
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SelectAddr(Address, Tmp2, offset);
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BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
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BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
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@@ -59,10 +59,16 @@ let Uses = [R28] in
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let Uses = [R29, R28] in {
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let Uses = [R29, R28] in {
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def LOAD_ADDR : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lda $RA,$DISP">; //Load address
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def LOAD_ADDR : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lda $RA,$DISP">; //Load address
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def LDQ_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldq $RA,$DISP">; //Load quadword
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def LDQ_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldq $RA,$DISP">; //Load quadword
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def LDW : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldw $RA,$DISP($RB)">; // Load sign-extended word
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def LDB : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldb $RA,$DISP($RB)">; //Load byte
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def LDS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lds $RA,$DISP">; //Load float
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def LDS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lds $RA,$DISP">; //Load float
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def LDT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldt $RA,$DISP">; //Load double
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def LDT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldt $RA,$DISP">; //Load double
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def LDL_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldl $RA,$DISP">; // Load sign-extended longword
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def LDBU_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldbu $RA,$DISP">; //Load zero-extended byte
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def LDWU_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldwu $RA,$DISP">; //Load zero-extended word
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def LDW_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldw $RA,$DISP">; // Load sign-extended word
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def LDB_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldb $RA,$DISP">; //Load byte
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def LDW : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldw $RA,$DISP($RB)">; // Load sign-extended word
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def LDB : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldb $RA,$DISP($RB)">; //Load byte
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def STB_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stb $RA,$DISP">; // Store byte
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def STB_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stb $RA,$DISP">; // Store byte
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def STW_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stw $RA,$DISP">; // Store word
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def STW_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stw $RA,$DISP">; // Store word
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