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Hexagon: Expand cttz, ctlz, and ctpop for now.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175783 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anshuman Dasgupta 2013-02-21 19:39:40 +00:00
parent 601158a18e
commit 6585d3b64b
2 changed files with 39 additions and 0 deletions
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5
lib/Target/Hexagon/HexagonISelLowering.cpp
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@ -1366,10 +1366,15 @@ HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
setOperationAction(ISD::CTPOP, MVT::i32, Expand);
setOperationAction(ISD::CTPOP, MVT::i64, Expand);
setOperationAction(ISD::CTTZ , MVT::i32, Expand);
setOperationAction(ISD::CTTZ , MVT::i64, Expand);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
setOperationAction(ISD::CTLZ , MVT::i32, Expand);
setOperationAction(ISD::CTLZ , MVT::i64, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
setOperationAction(ISD::ROTL , MVT::i32, Expand);
setOperationAction(ISD::ROTR , MVT::i32, Expand);
setOperationAction(ISD::BSWAP, MVT::i32, Expand);

34
test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll Normal file
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@ -0,0 +1,34 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; CHECK: r{{[0-9]+}}:{{[0-9]+}} |= lsr(r{{[0-9]+}}:{{[0-9]+}}, #4)
; CHECK: r{{[0-9]+}}:{{[0-9]+}} &= lsr(r{{[0-9]+}}:{{[0-9]+}}, #2)
; CHECK: r{{[0-9]+}} += lsr(r{{[0-9]+}}, #4)
define i32 @foo(i64 %a, i32 %b) nounwind {
entry:
%tmp0 = tail call i64 @llvm.ctlz.i64( i64 %a, i1 true )
%tmp1 = tail call i64 @llvm.cttz.i64( i64 %a, i1 true )
%tmp2 = tail call i32 @llvm.ctlz.i32( i32 %b, i1 true )
%tmp3 = tail call i32 @llvm.cttz.i32( i32 %b, i1 true )
%tmp4 = tail call i64 @llvm.ctpop.i64( i64 %a )
%tmp5 = tail call i32 @llvm.ctpop.i32( i32 %b )
%tmp6 = trunc i64 %tmp0 to i32
%tmp7 = trunc i64 %tmp1 to i32
%tmp8 = trunc i64 %tmp4 to i32
%tmp9 = add i32 %tmp6, %tmp7
%tmp10 = add i32 %tmp9, %tmp8
%tmp11 = add i32 %tmp10, %tmp2
%tmp12 = add i32 %tmp11, %tmp3
%tmp13 = add i32 %tmp12, %tmp5
ret i32 %tmp13
}
declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
declare i64 @llvm.cttz.i64(i64, i1) nounwind readnone
declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone
declare i64 @llvm.ctpop.i64(i64) nounwind readnone
declare i32 @llvm.ctpop.i32(i32) nounwind readnone