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legalizing the ret operation on f64 shouldn't introduce a new

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i64 bit convert needlessly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43116 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-10-18 06:17:07 +00:00
parent 7b714321df
commit 65a3323b0a
1 changed files with 6 additions and 4 deletions
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10
lib/Target/ARM/ARMISelLowering.cpp
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@ -670,10 +670,12 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
if (Op.getValueType() == MVT::f32) {
Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
} else if (Op.getValueType() == MVT::f64) {
// Recursively legalize f64 -> i64.
Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Op);
return DAG.getNode(ISD::RET, MVT::Other, Chain, Op,
DAG.getConstant(0, MVT::i32));
// Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
// available.
Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1);
SDOperand Sign = DAG.getConstant(0, MVT::i32);
return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign,
Op.getValue(1), Sign);
}
Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
if (DAG.getMachineFunction().liveout_empty())