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Support added for ctlz intrinsic, test case added.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54516 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2008-08-08 06:16:31 +00:00
parent fc65d38085
commit 65ad452536
4 changed files with 31 additions and 18 deletions
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4
lib/Target/Mips/MipsISelLowering.cpp
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@ -119,7 +119,6 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
setOperationAction(ISD::CTPOP, MVT::i32, Expand);
setOperationAction(ISD::CTTZ, MVT::i32, Expand);
setOperationAction(ISD::CTLZ, MVT::i32, Expand);
setOperationAction(ISD::ROTL, MVT::i32, Expand);
setOperationAction(ISD::ROTR, MVT::i32, Expand);
setOperationAction(ISD::BSWAP, MVT::i32, Expand);
@ -147,6 +146,9 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
}
if (!Subtarget->hasBitCount())
setOperationAction(ISD::CTLZ, MVT::i32, Expand);
setStackPointerRegisterToSaveRestore(Mips::SP);
computeRegisterProperties();
}

32
lib/Target/Mips/MipsInstrInfo.td
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@ -51,7 +51,8 @@ def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>;
//===----------------------------------------------------------------------===//
// Mips Instruction Predicate Definitions.
//===----------------------------------------------------------------------===//
def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
//===----------------------------------------------------------------------===//
// Mips Operand, Complex Patterns and Transformations Definitions.
@ -332,15 +333,6 @@ class MoveToLOHI<bits<6> func, string instr_asm>:
!strconcat(instr_asm, "\t$src"),
[], IIHiLo>;
// Count Leading Ones/Zeros in Word
class CountLeading<bits<6> func, string instr_asm>:
FR< 0x1c,
func,
(outs CPURegs:$dst),
(ins CPURegs:$src),
!strconcat(instr_asm, "\t$dst, $src"),
[], IIAlu>;
class EffectiveAddress<string instr_asm> :
FI<0x09,
(outs CPURegs:$dst),
@ -348,6 +340,13 @@ class EffectiveAddress<string instr_asm> :
instr_asm,
[(set CPURegs:$dst, addr:$addr)], IIAlu>;
// Count Leading Ones/Zeros in Word
class CountLeading<bits<6> func, string instr_asm, SDNode CountOp>:
FR< 0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
!strconcat(instr_asm, "\t$dst, $src"),
[(set CPURegs:$dst, (CountOp CPURegs:$src))], IIAlu>;
// Sign Extend in Register.
class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
FR< 0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
!strconcat(instr_asm, "\t$dst, $src"),
@ -494,6 +493,12 @@ let Predicates = [HasSEInReg] in {
def SEH : SignExtInReg<0x20, "seh", i16>;
}
/// Count Leading
let Predicates = [HasBitCount] in {
def CLZ : CountLeading<0b010110, "clz", ctlz>;
//def CLO : CountLeading<0b010110, "clo">;
}
/// No operation
let addr=0 in
def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
@ -504,13 +509,6 @@ let addr=0 in
// can be matched. It's similar to Sparc LEA_ADDRi
def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
// Count Leading
// CLO/CLZ are part of the newer MIPS32(tm) instruction
// set and not older Mips I keep this for future use
// though.
//def CLO : CountLeading<0x21, "clo">;
//def CLZ : CountLeading<0x20, "clz">;
// MADD*/MSUB* are not part of MipsI either.
//def MADD : MArithR<0x00, "madd">;
//def MADDU : MArithR<0x01, "maddu">;

1
lib/Target/Mips/MipsSubtarget.cpp
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@ -57,6 +57,7 @@ MipsSubtarget::MipsSubtarget(const TargetMachine &TM, const Module &M,
MipsArchVersion = Mips2;
HasVFPU = true; // Enables Allegrex Vector FPU (not supported yet)
HasSEInReg = true;
HasBitCount = true;
}
// Abicall is the default for O32 ABI and is ignored

12
test/CodeGen/Mips/2008-08-08-ctlz.ll Normal file
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@ -0,0 +1,12 @@
; RUN: llvm-as < %s | llc -march=mips | grep clz | count 1
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "mipsallegrexel-psp-elf"
define i32 @A0(i32 %u) nounwind {
entry:
call i32 @llvm.ctlz.i32( i32 %u )
ret i32 %0
}
declare i32 @llvm.ctlz.i32(i32) nounwind readnone