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https://github.com/c64scene-ar/llvm-6502.git
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Doxygenify some comments.
Clean up cpReg2MemMI and cpMem2RegMI, and doxygenify comments. Get rid of their uses of SETSW, which is a pseudoinstruction. We can't JIT-compile pseudoinstructions at the moment. This was blowing up 252.eon/jit, which has some HUGE stack frames. Reduce the uses of constantFitsInImmedField(). Consolidate some assertions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15899 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke
parent
883342c1e5
commit
66149920c6
@ -744,82 +744,80 @@ SparcV9RegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
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mvec.push_back(MI);
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}
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//---------------------------------------------------------------------------
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// Copy from a register to memory (i.e., Store). Register number must
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// be the unified register number
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//---------------------------------------------------------------------------
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/// cpReg2MemMI - Generate SparcV9 MachineInstrs to store a register
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/// (SrcReg) to memory, at [PtrReg + Offset]. Register numbers must be the
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/// unified register numbers. RegType must be the SparcV9 register type
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/// of SrcReg. When SrcReg is %ccr, scratchReg must be the
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/// number of a free integer register. The newly-generated MachineInstrs
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/// are appended to mvec.
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///
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void SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
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unsigned SrcReg, unsigned PtrReg, int Offset,
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int RegType, int scratchReg) const {
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unsigned OffReg = SparcV9::g4; // Use register g4 for holding large offsets
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bool useImmediateOffset = true;
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// If the Offset will not fit in the signed-immediate field, we put it in
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// register g4. This takes advantage of the fact that all the opcodes
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// used below have the same size immed. field.
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if (RegType != IntCCRegType
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&& !target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) {
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// Put the offset into a register. We could do this in fewer steps,
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// in some cases (see CreateSETSWConst()) but we're being lazy.
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MachineInstr *MI = BuildMI(V9::SETHI, 2).addZImm(Offset).addMReg(OffReg,
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MachineOperand::Def);
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MI->getOperand(0).markHi32();
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mvec.push_back(MI);
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MI = BuildMI(V9::ORi,3).addMReg(OffReg).addZImm(Offset).addMReg(OffReg,
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MachineOperand::Def);
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MI->getOperand(1).markLo32();
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mvec.push_back(MI);
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MI = BuildMI(V9::SRAi5,3).addMReg(OffReg).addZImm(0).addMReg(OffReg,
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MachineOperand::Def);
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mvec.push_back(MI);
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useImmediateOffset = false;
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}
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void
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SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
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unsigned SrcReg,
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unsigned PtrReg,
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int Offset, int RegType,
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int scratchReg) const {
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MachineInstr * MI = NULL;
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int OffReg = -1;
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// If the Offset will not fit in the signed-immediate field, find an
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// unused register to hold the offset value. This takes advantage of
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// the fact that all the opcodes used below have the same size immed. field.
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// Use the register allocator, PRA, to find an unused reg. at this MI.
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//
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if (RegType != IntCCRegType) // does not use offset below
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if (! target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) {
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#ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
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RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
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OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
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#else
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// Default to using register g4 for holding large offsets
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OffReg = getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
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SparcV9IntRegClass::g4);
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#endif
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assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
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mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
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}
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MachineInstr *MI = 0;
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switch (RegType) {
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case IntRegType:
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if (target.getInstrInfo()->constantFitsInImmedField(V9::STXi, Offset))
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if (useImmediateOffset)
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MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
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else
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MI = BuildMI(V9::STXr,3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
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break;
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case FPSingleRegType:
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if (target.getInstrInfo()->constantFitsInImmedField(V9::STFi, Offset))
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if (useImmediateOffset)
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MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
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else
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MI = BuildMI(V9::STFr, 3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
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break;
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case FPDoubleRegType:
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if (target.getInstrInfo()->constantFitsInImmedField(V9::STDFi, Offset))
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if (useImmediateOffset)
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MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
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else
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MI = BuildMI(V9::STDFr,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(OffReg);
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break;
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case IntCCRegType:
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assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory");
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assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
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MI = (BuildMI(V9::RDCCR, 2)
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.addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
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SparcV9IntCCRegClass::ccr))
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.addMReg(scratchReg, MachineOperand::Def));
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assert(scratchReg >= 0 && getRegType(scratchReg) == IntRegType
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&& "Need a scratch reg of integer type to load or store %ccr");
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MI = BuildMI(V9::RDCCR, 2).addMReg(SparcV9::ccr)
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.addMReg(scratchReg, MachineOperand::Def);
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mvec.push_back(MI);
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cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType);
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return;
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case SpecialRegType: // used only for %fsr itself.
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case FloatCCRegType: {
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unsigned fsrReg = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
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SparcV9SpecialRegClass::fsr);
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if (target.getInstrInfo()->constantFitsInImmedField(V9::STXFSRi, Offset))
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MI=BuildMI(V9::STXFSRi,3).addMReg(fsrReg).addMReg(PtrReg).addSImm(Offset);
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if (useImmediateOffset)
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MI = BuildMI(V9::STXFSRi,3).addMReg(SparcV9::fsr).addMReg(PtrReg)
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.addSImm(Offset);
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else
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MI=BuildMI(V9::STXFSRr,3).addMReg(fsrReg).addMReg(PtrReg).addMReg(OffReg);
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MI = BuildMI(V9::STXFSRr,3).addMReg(SparcV9::fsr).addMReg(PtrReg)
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.addMReg(OffReg);
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break;
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}
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default:
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@ -828,45 +826,42 @@ SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
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mvec.push_back(MI);
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}
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/// cpMem2RegMI - Generate SparcV9 MachineInstrs to load a register
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/// (DestReg) from memory, at [PtrReg + Offset]. Register numbers must be the
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/// unified register numbers. RegType must be the SparcV9 register type
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/// of DestReg. When DestReg is %ccr, scratchReg must be the
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/// number of a free integer register. The newly-generated MachineInstrs
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/// are appended to mvec.
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///
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void SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
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unsigned PtrReg, int Offset, unsigned DestReg,
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int RegType, int scratchReg) const {
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unsigned OffReg = SparcV9::g4; // Use register g4 for holding large offsets
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bool useImmediateOffset = true;
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//---------------------------------------------------------------------------
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// Copy from memory to a reg (i.e., Load) Register number must be the unified
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// register number
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//---------------------------------------------------------------------------
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void
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SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
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unsigned PtrReg,
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int Offset,
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unsigned DestReg,
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int RegType,
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int scratchReg) const {
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MachineInstr * MI = NULL;
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int OffReg = -1;
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// If the Offset will not fit in the signed-immediate field, find an
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// unused register to hold the offset value. This takes advantage of
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// the fact that all the opcodes used below have the same size immed. field.
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// Use the register allocator, PRA, to find an unused reg. at this MI.
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//
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if (RegType != IntCCRegType) // does not use offset below
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if (! target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) {
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#ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
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RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
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OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
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#else
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// Default to using register g4 for holding large offsets
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OffReg = getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
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SparcV9IntRegClass::g4);
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#endif
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assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
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mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
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}
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// If the Offset will not fit in the signed-immediate field, we put it in
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// register g4. This takes advantage of the fact that all the opcodes
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// used below have the same size immed. field.
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if (RegType != IntCCRegType
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&& !target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) {
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MachineInstr *MI = BuildMI(V9::SETHI, 2).addZImm(Offset).addMReg(OffReg,
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MachineOperand::Def);
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MI->getOperand(0).markHi32();
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mvec.push_back(MI);
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MI = BuildMI(V9::ORi,3).addMReg(OffReg).addZImm(Offset).addMReg(OffReg,
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MachineOperand::Def);
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MI->getOperand(1).markLo32();
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mvec.push_back(MI);
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MI = BuildMI(V9::SRAi5,3).addMReg(OffReg).addZImm(0).addMReg(OffReg,
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MachineOperand::Def);
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mvec.push_back(MI);
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useImmediateOffset = false;
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}
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MachineInstr *MI = 0;
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switch (RegType) {
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case IntRegType:
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if (target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset))
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if (useImmediateOffset)
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MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset)
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.addMReg(DestReg, MachineOperand::Def);
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else
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@ -875,7 +870,7 @@ SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
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break;
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case FPSingleRegType:
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if (target.getInstrInfo()->constantFitsInImmedField(V9::LDFi, Offset))
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if (useImmediateOffset)
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MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset)
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.addMReg(DestReg, MachineOperand::Def);
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else
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@ -884,7 +879,7 @@ SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
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break;
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case FPDoubleRegType:
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if (target.getInstrInfo()->constantFitsInImmedField(V9::LDDFi, Offset))
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if (useImmediateOffset)
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MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset)
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.addMReg(DestReg, MachineOperand::Def);
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else
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@ -893,26 +888,21 @@ SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
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break;
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case IntCCRegType:
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assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory");
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assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
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assert(scratchReg >= 0 && getRegType(scratchReg) == IntRegType
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&& "Need a scratch reg of integer type to load or store %ccr");
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cpMem2RegMI(mvec, PtrReg, Offset, scratchReg, IntRegType);
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MI = (BuildMI(V9::WRCCRr, 3)
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.addMReg(scratchReg)
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.addMReg(SparcV9IntRegClass::g0)
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.addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
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SparcV9IntCCRegClass::ccr), MachineOperand::Def));
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MI = BuildMI(V9::WRCCRr, 3).addMReg(scratchReg).addMReg(SparcV9::g0)
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.addMReg(SparcV9::ccr, MachineOperand::Def);
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break;
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case SpecialRegType: // used only for %fsr itself
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case FloatCCRegType: {
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unsigned fsrRegNum = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
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SparcV9SpecialRegClass::fsr);
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if (target.getInstrInfo()->constantFitsInImmedField(V9::LDXFSRi, Offset))
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if (useImmediateOffset)
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MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset)
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.addMReg(fsrRegNum, MachineOperand::UseAndDef);
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.addMReg(SparcV9::fsr, MachineOperand::Def);
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else
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MI = BuildMI(V9::LDXFSRr, 3).addMReg(PtrReg).addMReg(OffReg)
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.addMReg(fsrRegNum, MachineOperand::UseAndDef);
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.addMReg(SparcV9::fsr, MachineOperand::Def);
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break;
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}
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default:
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