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tidy up trailing whitespace and an 80 column violation.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112746 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-09-01 21:48:06 +00:00
parent b0a57210a4
commit 662fb77687
1 changed files with 25 additions and 24 deletions
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49
lib/CodeGen/RegAllocLinearScan.cpp
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@ -87,7 +87,7 @@ namespace {
"to skip."), "to skip."),
cl::init(0), cl::init(0),
cl::Hidden); cl::Hidden);
struct RALinScan : public MachineFunctionPass { struct RALinScan : public MachineFunctionPass {
static char ID; static char ID;
RALinScan() : MachineFunctionPass(ID) { RALinScan() : MachineFunctionPass(ID) {
@ -383,7 +383,7 @@ void RALinScan::ComputeRelatedRegClasses() {
for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end(); for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
I != E; ++I) { I != E; ++I) {
HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0; HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I]; const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
if (PRC) { if (PRC) {
// Already processed this register. Just make sure we know that // Already processed this register. Just make sure we know that
@ -394,7 +394,7 @@ void RALinScan::ComputeRelatedRegClasses() {
} }
} }
} }
// Second pass, now that we know conservatively what register classes each reg // Second pass, now that we know conservatively what register classes each reg
// belongs to, add info about aliases. We don't need to do this for targets // belongs to, add info about aliases. We don't need to do this for targets
// without register aliases. // without register aliases.
@ -495,9 +495,9 @@ bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
vrm_ = &getAnalysis<VirtRegMap>(); vrm_ = &getAnalysis<VirtRegMap>();
if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter()); if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
spiller_.reset(createSpiller(*this, *mf_, *vrm_)); spiller_.reset(createSpiller(*this, *mf_, *vrm_));
initIntervalSets(); initIntervalSets();
linearScan(); linearScan();
@ -551,7 +551,7 @@ void RALinScan::linearScan() {
// linear scan algorithm // linear scan algorithm
DEBUG({ DEBUG({
dbgs() << "********** LINEAR SCAN **********\n" dbgs() << "********** LINEAR SCAN **********\n"
<< "********** Function: " << "********** Function: "
<< mf_->getFunction()->getName() << '\n'; << mf_->getFunction()->getName() << '\n';
printIntervals("fixed", fixed_.begin(), fixed_.end()); printIntervals("fixed", fixed_.begin(), fixed_.end());
}); });
@ -773,7 +773,8 @@ FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
return IP.end(); return IP.end();
} }
static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, SlotIndex Point){ static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V,
SlotIndex Point){
for (unsigned i = 0, e = V.size(); i != e; ++i) { for (unsigned i = 0, e = V.size(); i != e; ++i) {
RALinScan::IntervalPtr &IP = V[i]; RALinScan::IntervalPtr &IP = V[i];
LiveInterval::iterator I = std::upper_bound(IP.first->begin(), LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
@ -845,7 +846,7 @@ void RALinScan::findIntervalsToSpill(LiveInterval *cur,
dbgs() << tri_->getName(Candidates[i].first) << " "; dbgs() << tri_->getName(Candidates[i].first) << " ";
dbgs() << "\n"; dbgs() << "\n";
}); });
// Calculate the number of conflicts of each candidate. // Calculate the number of conflicts of each candidate.
for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) { for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
unsigned Reg = i->first->reg; unsigned Reg = i->first->reg;
@ -1015,7 +1016,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
assert(TargetRegisterInfo::isVirtualRegister(Reg) && assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
"Can only allocate virtual registers!"); "Can only allocate virtual registers!");
const TargetRegisterClass *RegRC = mri_->getRegClass(Reg); const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
// If this is not in a related reg class to the register we're allocating, // If this is not in a related reg class to the register we're allocating,
// don't check it. // don't check it.
if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader && if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
cur->overlapsFrom(*i->first, i->second-1)) { cur->overlapsFrom(*i->first, i->second-1)) {
@ -1024,7 +1025,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight)); SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
} }
} }
// Speculatively check to see if we can get a register right now. If not, // Speculatively check to see if we can get a register right now. If not,
// we know we won't be able to by adding more constraints. If so, we can // we know we won't be able to by adding more constraints. If so, we can
// check to see if it is valid. Doing an exhaustive search of the fixed_ list // check to see if it is valid. Doing an exhaustive search of the fixed_ list
@ -1039,7 +1040,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
SmallSet<unsigned, 8> RegAliases; SmallSet<unsigned, 8> RegAliases;
for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS) for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
RegAliases.insert(*AS); RegAliases.insert(*AS);
bool ConflictsWithFixed = false; bool ConflictsWithFixed = false;
for (unsigned i = 0, e = fixed_.size(); i != e; ++i) { for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
IntervalPtr &IP = fixed_[i]; IntervalPtr &IP = fixed_[i];
@ -1059,7 +1060,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
} }
} }
} }
// Okay, the register picked by our speculative getFreePhysReg call turned // Okay, the register picked by our speculative getFreePhysReg call turned
// out to be in use. Actually add all of the conflicting fixed registers to // out to be in use. Actually add all of the conflicting fixed registers to
// regUse_ so we can do an accurate query. // regUse_ so we can do an accurate query.
@ -1071,7 +1072,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
LiveInterval *I = IP.first; LiveInterval *I = IP.first;
const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg]; const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader && if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
I->endIndex() > StartPosition) { I->endIndex() > StartPosition) {
LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition); LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
IP.second = II; IP.second = II;
@ -1090,11 +1091,11 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
physReg = getFreePhysReg(cur); physReg = getFreePhysReg(cur);
} }
} }
// Restore the physical register tracker, removing information about the // Restore the physical register tracker, removing information about the
// future. // future.
restoreRegUses(); restoreRegUses();
// If we find a free register, we are done: assign this virtual to // If we find a free register, we are done: assign this virtual to
// the free physical register and add this interval to the active // the free physical register and add this interval to the active
// list. // list.
@ -1109,7 +1110,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
UpgradeRegister(physReg); UpgradeRegister(physReg);
if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) { if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
// "Downgrade" physReg to try to keep physReg from being allocated until // "Downgrade" physReg to try to keep physReg from being allocated until
// the next reload from the same SS is allocated. // the next reload from the same SS is allocated.
mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg); mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
DowngradeRegister(cur, physReg); DowngradeRegister(cur, physReg);
} }
@ -1122,7 +1123,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
for (std::vector<std::pair<unsigned, float> >::iterator for (std::vector<std::pair<unsigned, float> >::iterator
I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I) I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
updateSpillWeights(SpillWeights, I->first, I->second, RC); updateSpillWeights(SpillWeights, I->first, I->second, RC);
// for each interval in active, update spill weights. // for each interval in active, update spill weights.
for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end(); for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
i != e; ++i) { i != e; ++i) {
@ -1132,7 +1133,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
reg = vrm_->getPhys(reg); reg = vrm_->getPhys(reg);
updateSpillWeights(SpillWeights, reg, i->first->weight, RC); updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
} }
DEBUG(dbgs() << "\tassigning stack slot at interval "<< *cur << ":\n"); DEBUG(dbgs() << "\tassigning stack slot at interval "<< *cur << ":\n");
// Find a register to spill. // Find a register to spill.
@ -1152,7 +1153,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
Found = true; Found = true;
RegsWeights.push_back(std::make_pair(reg, regWeight)); RegsWeights.push_back(std::make_pair(reg, regWeight));
} }
// If we didn't find a register that is spillable, try aliases? // If we didn't find a register that is spillable, try aliases?
if (!Found) { if (!Found) {
for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_), for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
@ -1281,7 +1282,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
// The earliest start of a Spilled interval indicates up to where // The earliest start of a Spilled interval indicates up to where
// in handled we need to roll back // in handled we need to roll back
assert(!spillIs.empty() && "No spill intervals?"); assert(!spillIs.empty() && "No spill intervals?");
SlotIndex earliestStart = spillIs[0]->beginIndex(); SlotIndex earliestStart = spillIs[0]->beginIndex();
// Spill live intervals of virtual regs mapped to the physical register we // Spill live intervals of virtual regs mapped to the physical register we
@ -1484,17 +1485,17 @@ unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
unsigned RALinScan::getFreePhysReg(LiveInterval *cur) { unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
SmallVector<unsigned, 256> inactiveCounts; SmallVector<unsigned, 256> inactiveCounts;
unsigned MaxInactiveCount = 0; unsigned MaxInactiveCount = 0;
const TargetRegisterClass *RC = mri_->getRegClass(cur->reg); const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC); const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end(); for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
i != e; ++i) { i != e; ++i) {
unsigned reg = i->first->reg; unsigned reg = i->first->reg;
assert(TargetRegisterInfo::isVirtualRegister(reg) && assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!"); "Can only allocate virtual registers!");
// If this is not in a related reg class to the register we're allocating, // If this is not in a related reg class to the register we're allocating,
// don't check it. // don't check it.
const TargetRegisterClass *RegRC = mri_->getRegClass(reg); const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) { if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
@ -1511,7 +1512,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
unsigned Preference = vrm_->getRegAllocPref(cur->reg); unsigned Preference = vrm_->getRegAllocPref(cur->reg);
if (Preference) { if (Preference) {
DEBUG(dbgs() << "(preferred: " << tri_->getName(Preference) << ") "); DEBUG(dbgs() << "(preferred: " << tri_->getName(Preference) << ") ");
if (isRegAvail(Preference) && if (isRegAvail(Preference) &&
RC->contains(Preference)) RC->contains(Preference))
return Preference; return Preference;
} }