mirror of
https://github.com/c64scene-ar/llvm-6502.git
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remove some old autoupgrade logic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145167 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
9d5f6ccd26
commit
663aebf8d6
@ -107,38 +107,6 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
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}
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break;
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case 'x': {
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const char *NewFnName = NULL;
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// This fixes the poorly named crc32 intrinsics.
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if (Name == "x86.sse42.crc32.8")
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NewFnName = "llvm.x86.sse42.crc32.32.8";
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else if (Name == "x86.sse42.crc32.16")
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NewFnName = "llvm.x86.sse42.crc32.32.16";
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else if (Name == "x86.sse42.crc32.32")
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NewFnName = "llvm.x86.sse42.crc32.32.32";
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else if (Name == "x86.sse42.crc64.8")
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NewFnName = "llvm.x86.sse42.crc32.64.8";
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else if (Name == "x86.sse42.crc64.64")
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NewFnName = "llvm.x86.sse42.crc32.64.64";
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if (NewFnName) {
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F->setName(NewFnName);
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NewFn = F;
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return true;
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}
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// Calls to these instructions are transformed into unaligned loads.
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if (Name == "x86.sse.loadu.ps" || Name == "x86.sse2.loadu.dq" ||
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Name == "x86.sse2.loadu.pd")
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return true;
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// Calls to these instructions are transformed into nontemporal stores.
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if (Name == "x86.sse.movnt.ps" || Name == "x86.sse2.movnt.dq" ||
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Name == "x86.sse2.movnt.pd" || Name == "x86.sse2.movnt.i")
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return true;
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break;
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}
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}
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// This may not belong here. This function is effectively being overloaded
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@ -176,54 +144,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
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assert(F && "CallInst has no function associated with it.");
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if (!NewFn) {
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if (F->getName() == "llvm.x86.sse.loadu.ps" ||
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F->getName() == "llvm.x86.sse2.loadu.dq" ||
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F->getName() == "llvm.x86.sse2.loadu.pd") {
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// Convert to a native, unaligned load.
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Type *VecTy = CI->getType();
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Type *IntTy = IntegerType::get(C, 128);
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IRBuilder<> Builder(C);
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Builder.SetInsertPoint(CI->getParent(), CI);
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Value *BC = Builder.CreateBitCast(CI->getArgOperand(0),
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PointerType::getUnqual(IntTy),
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"cast");
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LoadInst *LI = Builder.CreateLoad(BC, CI->getName());
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LI->setAlignment(1); // Unaligned load.
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BC = Builder.CreateBitCast(LI, VecTy, "new.cast");
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// Fix up all the uses with our new load.
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if (!CI->use_empty())
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CI->replaceAllUsesWith(BC);
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// Remove intrinsic.
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CI->eraseFromParent();
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} else if (F->getName() == "llvm.x86.sse.movnt.ps" ||
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F->getName() == "llvm.x86.sse2.movnt.dq" ||
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F->getName() == "llvm.x86.sse2.movnt.pd" ||
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F->getName() == "llvm.x86.sse2.movnt.i") {
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IRBuilder<> Builder(C);
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Builder.SetInsertPoint(CI->getParent(), CI);
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Module *M = F->getParent();
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SmallVector<Value *, 1> Elts;
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Elts.push_back(ConstantInt::get(Type::getInt32Ty(C), 1));
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MDNode *Node = MDNode::get(C, Elts);
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Value *Arg0 = CI->getArgOperand(0);
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Value *Arg1 = CI->getArgOperand(1);
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// Convert the type of the pointer to a pointer to the stored type.
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Value *BC = Builder.CreateBitCast(Arg0,
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PointerType::getUnqual(Arg1->getType()),
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"cast");
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StoreInst *SI = Builder.CreateStore(Arg1, BC);
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SI->setMetadata(M->getMDKindID("nontemporal"), Node);
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SI->setAlignment(16);
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// Remove intrinsic.
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CI->eraseFromParent();
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} else if (F->getName().startswith("llvm.atomic.cmp.swap")) {
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if (F->getName().startswith("llvm.atomic.cmp.swap")) {
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IRBuilder<> Builder(C);
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Builder.SetInsertPoint(CI->getParent(), CI);
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Value *Val = Builder.CreateAtomicCmpXchg(CI->getArgOperand(0),
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@ -2,37 +2,6 @@
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; RUN: llvm-as < %s | llvm-dis | FileCheck %s
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declare <4 x float> @llvm.x86.sse.loadu.ps(i8*) nounwind readnone
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declare <16 x i8> @llvm.x86.sse2.loadu.dq(i8*) nounwind readnone
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declare <2 x double> @llvm.x86.sse2.loadu.pd(double*) nounwind readnone
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define void @test_loadu(i8* %a, double* %b) {
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%v0 = call <4 x float> @llvm.x86.sse.loadu.ps(i8* %a)
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%v1 = call <16 x i8> @llvm.x86.sse2.loadu.dq(i8* %a)
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%v2 = call <2 x double> @llvm.x86.sse2.loadu.pd(double* %b)
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; CHECK: load i128* {{.*}}, align 1
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; CHECK: load i128* {{.*}}, align 1
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; CHECK: load i128* {{.*}}, align 1
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ret void
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}
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declare void @llvm.x86.sse.movnt.ps(i8*, <4 x float>) nounwind readnone
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declare void @llvm.x86.sse2.movnt.dq(i8*, <2 x double>) nounwind readnone
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declare void @llvm.x86.sse2.movnt.pd(i8*, <2 x double>) nounwind readnone
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declare void @llvm.x86.sse2.movnt.i(i8*, i32) nounwind readnone
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define void @f(<4 x float> %A, i8* %B, <2 x double> %C, i32 %D) {
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; CHECK: store{{.*}}nontemporal
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call void @llvm.x86.sse.movnt.ps(i8* %B, <4 x float> %A)
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; CHECK: store{{.*}}nontemporal
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call void @llvm.x86.sse2.movnt.dq(i8* %B, <2 x double> %C)
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; CHECK: store{{.*}}nontemporal
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call void @llvm.x86.sse2.movnt.pd(i8* %B, <2 x double> %C)
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; CHECK: store{{.*}}nontemporal
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call void @llvm.x86.sse2.movnt.i(i8* %B, i32 %D)
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ret void
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}
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declare void @llvm.prefetch(i8*, i32, i32) nounwind
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define void @p(i8* %ptr) {
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@ -1,44 +0,0 @@
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; Check to make sure old CRC32 intrinsics are auto-upgraded correctly.
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; Auto-upgrade happens when parsing a .bc or a .ll file. Thus, leave the test
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; case as a .ll file so we can see what's going on.
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;
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; Rdar: 9472944
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;
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; RUN: opt < %s -S | FileCheck %s
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; crc32.8 should upgrade to crc32.32.8
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; CHECK: i32 @llvm.x86.sse42.crc32.32.8(
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; CHECK-NOT: i32 @llvm.x86.sse42.crc32.8(
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; crc32.16 should upgrade to crc32.32.16
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; CHECK: i32 @llvm.x86.sse42.crc32.32.16(
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; CHECK-NOT: i32 @llvm.x86.sse42.crc32.16(
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; crc32.32 should upgrade to crc32.32.32
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; CHECK: i32 @llvm.x86.sse42.crc32.32.32(
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; CHECK-NOT: i32 @llvm.x86.sse42.crc32.32(
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; crc64.8 should upgrade to crc32.64.8
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; CHECK: i64 @llvm.x86.sse42.crc32.64.8(
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; CHECK-NOT: i64 @llvm.x86.sse42.crc64.8(
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; crc64.64 should upgrade to crc32.64.64
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; CHECK: i64 @llvm.x86.sse42.crc32.64.64(
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; CHECK-NOT: i64 @llvm.x86.sse42.crc64.64(
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define void @foo() nounwind readnone ssp {
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entry:
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%0 = call i32 @llvm.x86.sse42.crc32.8(i32 0, i8 0)
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%1 = call i32 @llvm.x86.sse42.crc32.16(i32 0, i16 0)
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%2 = call i32 @llvm.x86.sse42.crc32.32(i32 0, i32 0)
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%3 = call i64 @llvm.x86.sse42.crc64.8(i64 0, i8 0)
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%4 = call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 0)
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ret void
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}
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declare i32 @llvm.x86.sse42.crc32.8(i32, i8) nounwind readnone
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declare i32 @llvm.x86.sse42.crc32.16(i32, i16) nounwind readnone
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declare i32 @llvm.x86.sse42.crc32.32(i32, i32) nounwind readnone
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declare i64 @llvm.x86.sse42.crc64.8(i64, i8) nounwind readnone
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declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone
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@ -245,34 +245,6 @@ define <2 x double> @test_x86_sse2_div_sd(<2 x double> %a0, <2 x double> %a1) {
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declare <2 x double> @llvm.x86.sse2.div.sd(<2 x double>, <2 x double>) nounwind readnone
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define <16 x i8> @test_x86_sse2_loadu_dq(i8* %a0) {
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; CHECK: movl
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; CHECK: vmovups
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%res = call <16 x i8> @llvm.x86.sse2.loadu.dq(i8* %a0) ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %res
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}
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declare <16 x i8> @llvm.x86.sse2.loadu.dq(i8*) nounwind readonly
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define <2 x double> @test_x86_sse2_loadu_pd(i8* %a0) {
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; CHECK: movl
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; CHECK: vmovups
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%res = call <2 x double> @llvm.x86.sse2.loadu.pd(i8* %a0) ; <<2 x double>> [#uses=1]
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.sse2.loadu.pd(i8*) nounwind readonly
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define void @test_x86_sse2_maskmov_dqu(<16 x i8> %a0, <16 x i8> %a1, i8* %a2) {
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; CHECK: pushl
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; CHECK: movl
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; CHECK: vmaskmovdqu
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; CHECK: popl
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call void @llvm.x86.sse2.maskmov.dqu(<16 x i8> %a0, <16 x i8> %a1, i8* %a2)
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ret void
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}
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declare void @llvm.x86.sse2.maskmov.dqu(<16 x i8>, <16 x i8>, i8*) nounwind
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define <2 x double> @test_x86_sse2_max_pd(<2 x double> %a0, <2 x double> %a1) {
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; CHECK: vmaxpd
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@ -314,28 +286,6 @@ define i32 @test_x86_sse2_movmsk_pd(<2 x double> %a0) {
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declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>) nounwind readnone
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define void @test_x86_sse2_movnt_dq(i8* %a0, <2 x i64> %a1) {
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; CHECK: test_x86_sse2_movnt_dq
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; CHECK: movl
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; CHECK: vmovntdq
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; add operation forces the execution domain.
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%a2 = add <2 x i64> %a1, <i64 1, i64 1>
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call void @llvm.x86.sse2.movnt.dq(i8* %a0, <2 x i64> %a2)
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ret void
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}
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declare void @llvm.x86.sse2.movnt.dq(i8*, <2 x i64>) nounwind
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define void @test_x86_sse2_movnt_pd(i8* %a0, <2 x double> %a1) {
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; CHECK test_x86_sse2_movnt_pd
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; CHECK: movl
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; CHECK: vmovntpd
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; fadd operation forces the execution domain.
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%a2 = fadd <2 x double> %a1, <double 0x0, double 0x4200000000000000>
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call void @llvm.x86.sse2.movnt.pd(i8* %a0, <2 x double> %a2)
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ret void
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}
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declare void @llvm.x86.sse2.movnt.pd(i8*, <2 x double>) nounwind
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define <2 x double> @test_x86_sse2_mul_sd(<2 x double> %a0, <2 x double> %a1) {
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@ -967,14 +917,6 @@ define <4 x float> @test_x86_sse41_insertps(<4 x float> %a0, <4 x float> %a1) {
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declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
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define <2 x i64> @test_x86_sse41_movntdqa(i8* %a0) {
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; CHECK: movl
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; CHECK: vmovntdqa
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%res = call <2 x i64> @llvm.x86.sse41.movntdqa(i8* %a0) ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %res
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}
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declare <2 x i64> @llvm.x86.sse41.movntdqa(i8*) nounwind readonly
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define <8 x i16> @test_x86_sse41_mpsadbw(<16 x i8> %a0, <16 x i8> %a1) {
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; CHECK: vmpsadbw
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@ -1524,14 +1466,6 @@ define void @test_x86_sse_ldmxcsr(i8* %a0) {
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declare void @llvm.x86.sse.ldmxcsr(i8*) nounwind
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define <4 x float> @test_x86_sse_loadu_ps(i8* %a0) {
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; CHECK: movl
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; CHECK: vmovups
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%res = call <4 x float> @llvm.x86.sse.loadu.ps(i8* %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.loadu.ps(i8*) nounwind readonly
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define <4 x float> @test_x86_sse_max_ps(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: vmaxps
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@ -1573,14 +1507,6 @@ define i32 @test_x86_sse_movmsk_ps(<4 x float> %a0) {
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declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>) nounwind readnone
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define void @test_x86_sse_movnt_ps(i8* %a0, <4 x float> %a1) {
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; CHECK: movl
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; CHECK: vmovntps
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call void @llvm.x86.sse.movnt.ps(i8* %a0, <4 x float> %a1)
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ret void
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}
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declare void @llvm.x86.sse.movnt.ps(i8*, <4 x float>) nounwind
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define <4 x float> @test_x86_sse_mul_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: vmulss
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@ -2019,34 +1945,6 @@ define <32 x i8> @test_x86_avx_ldu_dq_256(i8* %a0) {
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declare <32 x i8> @llvm.x86.avx.ldu.dq.256(i8*) nounwind readonly
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define <32 x i8> @test_x86_avx_loadu_dq_256(i8* %a0) {
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; CHECK: vmovdqu
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%a1 = call <32 x i8> @llvm.x86.avx.loadu.dq.256(i8* %a0) ; <<32 x i8>> [#uses=1]
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; add operation forces the execution domain.
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%res = add <32 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
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ret <32 x i8> %res
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}
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declare <32 x i8> @llvm.x86.avx.loadu.dq.256(i8*) nounwind readonly
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define <4 x double> @test_x86_avx_loadu_pd_256(i8* %a0) {
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; CHECK: vmovupd
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%a1 = call <4 x double> @llvm.x86.avx.loadu.pd.256(i8* %a0) ; <<4 x double>> [#uses=1]
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; add operation forces the execution domain.
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%res = fadd <4 x double> %a1, <double 0x0, double 0x0, double 0x0, double 0x0>
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ret <4 x double> %res
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}
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declare <4 x double> @llvm.x86.avx.loadu.pd.256(i8*) nounwind readonly
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define <8 x float> @test_x86_avx_loadu_ps_256(i8* %a0) {
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; CHECK: vmovups
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%res = call <8 x float> @llvm.x86.avx.loadu.ps.256(i8* %a0) ; <<8 x float>> [#uses=1]
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ret <8 x float> %res
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}
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declare <8 x float> @llvm.x86.avx.loadu.ps.256(i8*) nounwind readonly
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define <2 x double> @test_x86_avx_maskload_pd(i8* %a0, <2 x double> %a1) {
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; CHECK: vmaskmovpd
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%res = call <2 x double> @llvm.x86.avx.maskload.pd(i8* %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
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@ -2159,32 +2057,10 @@ define i32 @test_x86_avx_movmsk_ps_256(<8 x float> %a0) {
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declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) nounwind readnone
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define void @test_x86_avx_movnt_dq_256(i8* %a0, <4 x i64> %a1) {
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; CHECK: vmovntdq
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; add operation forces the execution domain.
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%a2 = add <4 x i64> %a1, <i64 1, i64 1, i64 1, i64 1>
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call void @llvm.x86.avx.movnt.dq.256(i8* %a0, <4 x i64> %a2)
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ret void
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}
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declare void @llvm.x86.avx.movnt.dq.256(i8*, <4 x i64>) nounwind
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define void @test_x86_avx_movnt_pd_256(i8* %a0, <4 x double> %a1) {
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; CHECK: vmovntpd
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%a2 = fadd <4 x double> %a1, <double 0x0, double 0x0, double 0x0, double 0x0>
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call void @llvm.x86.avx.movnt.pd.256(i8* %a0, <4 x double> %a2)
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ret void
|
||||
}
|
||||
declare void @llvm.x86.avx.movnt.pd.256(i8*, <4 x double>) nounwind
|
||||
|
||||
|
||||
define void @test_x86_avx_movnt_ps_256(i8* %a0, <8 x float> %a1) {
|
||||
; CHECK: vmovntps
|
||||
call void @llvm.x86.avx.movnt.ps.256(i8* %a0, <8 x float> %a1)
|
||||
ret void
|
||||
}
|
||||
declare void @llvm.x86.avx.movnt.ps.256(i8*, <8 x float>) nounwind
|
||||
|
||||
|
||||
define i32 @test_x86_avx_ptestc_256(<4 x i64> %a0, <4 x i64> %a1) {
|
||||
; CHECK: vptest
|
||||
|
||||
Loading…
Reference in New Issue
Block a user